TY  - CHAP
U1  - Konferenzveröffentlichung
A1  - Gerlach, Andreas
A1  - Scheible, Jürgen
A1  - Rosahl, Thoralf
A1  - Eitrich, Frank-Thomas
T1  - A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example
T2  - Proceedings of the 2017 Design, Automation & Test in Europe (DATE) : 27-31 March 2017, Swisstech, Lausanne, Switzerland
N2  - We present a new methodology for automatic selection and sizing of analog circuits demonstrated on the OTA circuit class. The methodology consists of two steps: a generic topology selection method supported by a “part-sizing” process and subsequent final sizing. The circuit topologies provided by a reuse library are classified in a topology tree. The appropriate topology is selected by traversing the topology tree starting at the root node. The decision at each node is gained from the result of the part-sizing, which is in fact a node-specific set of simulations. The final sizing is a simulation-based optimization. We significantly reduce the overall simulation effort compared to a classical simulation-based optimization by combining the topology selection with the part-sizing process in the selection loop. The result is an interactive user friendly system, which eases the analog designer’s work significantly when compared to typical industrial practice in analog circuit design. The topology selection method and sizing process are implemented as a tool into a typical analog design environment. The design productivity improvement achievable by our method is shown by a comparison to other design automation approaches.
Y1  - 2017
SN  - 978-3-9815370-8-6
SB  - 978-3-9815370-8-6
U6  - https://doi.org/10.23919/DATE.2017.7927115
DO  - https://doi.org/10.23919/DATE.2017.7927115
SP  - 898
EP  - 901
S1  - 4
PB  - IEEE
CY  - Piscataway, NJ
ER  -