TY  - CHAP
U1  - Konferenzveröffentlichung
A1  - Langner, Kerstin
A1  - Scheible, Jürgen
ED  - Pennisi, Salvatore
T1  - Formal verification of a transistor PCell
T2  - PRIME 2017 : 13th Conference on PH.D. Research in Microelectronics and Eletronics : conference proceedings : 12th-15th June 2017, Giardini Naxos, Taormina, Italy
N2  - Layout generators, commonly denoted as PCells (parameterized cells), play an important role in the layout design of analog ICs (integrated circuits). PCells can automatically create parts of a layout, whose properties are controlled by the PCell parameters. Any layout, whether hand-crafted or automatically generated, has to be verified against design rules using a DRC (design rule check) in order to assure proper functionality and producibility. Due to the growing complexity of today’s PCells it would be beneficial if a PCell itself could be ensured to produce DRC clean layouts for any allowed parameter values, i.e. a formal verification of the PCell’s code rather than checking all possible instances of the PCell. In this paper we demonstrate the feasibility of such a formal PCell verification for a simple NMOS transistor PCell. The set from which the parameter values can be chosen was found during the verification process.
KW  - layout generator
KW  - PCell
KW  - formal verification
KW  - DRC compliance
Y1  - 2017
SN  - 978-1-5090-6508-0
SB  - 978-1-5090-6508-0
U6  - https://doi.org/10.1109/PRIME.2017.7974143
DO  - https://doi.org/10.1109/PRIME.2017.7974143
SP  - 205
EP  - 208
S1  - 4
PB  - IEEE
CY  - Piscataway, NJ
ER  -