TY  - CHAP
U1  - Konferenzveröffentlichung
A1  - Schindler, Alexis
A1  - Koeppl, Benno
A1  - Wicht, Bernhard
A1  - Gröger, Johannes
T1  - 10ns variable current gate driver with control loop for optimized gate current timing and level control for in-transition slope shaping
T2  - APEC 2017 : Thirty Second Annual IEEE Applied Power Electronics Conference and Exposition : March 26-30, 2017, Tampa, Florida
N2  - Modern power transistors are able to switch at very high transition speed, which can cause EMC violations and overshoot. This is addressed by a gate driver with variable gate current, which is able to control the transition speed. The key idea is that the gate driver can influence the di/dt and dv/dt transition separately and optimize whichever transition promises the highest improvement while keeping switching losses low. To account for changes in the load current, supply voltage, etc., a control loop is required in the driver to ensure optimized switching. In this paper, an efficient control scheme for an automotive gate driver with variable output current capability is presented. The effectiveness of the control loop is demonstrated for a MOSFET bridge consisting of OptiMOS-T2™devices with a total gate charge of 39nC. This bridge setup shows dv/dt transitions between 50 to 1000ns, depending on driving current. The driver is able to switch between gate current levels of 1 to 500mA in 10/15ns (rising/falling transition). With the implemented control loop the driver is measured to significantly reduce the ringing and thereby reduce device stress and electromagnetic emissions while keeping switching losses 52% lower than with a constant current driver.
Y1  - 2017
SN  - 978-1-5090-5366-7
SB  - 978-1-5090-5366-7
U6  - https://doi.org/10.1109/APEC.2017.7931210
DO  - https://doi.org/10.1109/APEC.2017.7931210
SP  - 3570
EP  - 3575
S1  - 6
PB  - IEEE
CY  - Piscataway, NJ
ER  -