TY  - CHAP
U1  - Konferenzveröffentlichung
A1  - Marolt, Daniel
A1  - Scheible, Jürgen
A1  - Jerke, Göran
A1  - Marolt, Vinko
ED  - Forster, Gerhard
T1  - CAPABLE : a layout automation framework for analog IC design
T2  - MPC / Multi-Projekt-Chip-Gruppe Baden-Württemberg : Tagungsband zum Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg ; 54. Workshop on Microelectronics, 09.-10. Juli 2015, Hochschule Ulm, Germany
N2  - In practice, the use of layout PCells for analog IC design has not advanced beyond primitive devices and simple modules. This paper introduces a Constraint-Administered PCell-Applying Blocklevel Layout Engine (CAPABLE) which permits PCells to access their context, thus enabling a true "bottom-up" development of complex parameterized modules. These modules are integrated into the design flow with design constraints and applied by an execution cockpit via an automatically built layout script. The practical purpose of CAPABLE is to easily generate full-custom block layouts for given schematic circuits. Perspectively, our results inspire a whole new conception of PCells that can not only act (on demand), but also react (to environmental changes) and interact (with each other).
KW  - analog IC design
KW  - layout automation
KW  - parameterized cells
KW  - design constraints
KW  - bottom- up design
Y1  - 2015
U6  - https://nbn-resolving.org/urn:nbn:de:bsz:rt2-opus4-8324
UN  - https://nbn-resolving.org/urn:nbn:de:bsz:rt2-opus4-8324
UR  - https://www.mpc-gruppe.de/workshopbaende
SN  - 1868-9221
SS  - 1868-9221
SP  - 49
EP  - 59
S1  - 11
PB  - Hochschule Ulm
CY  - Ulm
ER  -