TY - CHAP U1 - Konferenzveröffentlichung A1 - Schweikardt, Matthias A1 - Uhlmann, Yannick A1 - Leber, Florian A1 - Scheible, Jürgen A1 - Habal, Husni T1 - A generic procedural generator for sizing of analog integrated circuits T2 - PRIME 19 : 15 - 18 July, Lausanne, Switzerland : 15th Conference on PhD Research in Microelectornics and Electronics (PRIME 2019) : conference proceedings N2 - In this paper, we address the novel EDP (Expert Design Plan) principle for procedural design automation of analog integrated circuits, which captures the knowledge-based design strategy of human circuit designers in an executable script, making it reusable. We present the EDP Player, which enables the creation and execution of EDPs for arbitrary circuits in the Cadence® Virtuoso® Design Environment. The tool provides a generic version of an instruction set, called EDPL (EDPLanguage), enabling emulation of a typical manual analog sizing flow. To automate the design of a Miller Operational Amplifier and to create variants of a Smart Power IC, several EDPs were implemented using this tool. Employing these EDPs leads to a strong reduction of design time without compromising design quality or reliability. KW - procedure KW - generator KW - expert design plan KW - electronic design automation KW - smart power ic KW - miller operational amplifier Y1 - 2019 SN - 978-1-7281-3549-6 SB - 978-1-7281-3549-6 U6 - https://doi.org/10.1109/PRIME.2019.8787743 DO - https://doi.org/10.1109/PRIME.2019.8787743 SP - 17 EP - 20 S1 - 4 PB - IEEE CY - Piscataway, NJ ER -