Optimizing PCB stackups for enhanced GaN transistor performance in high-power applications
- This paper explores specialized PCB stackups to enhance GaN transistor performance in applications up to 10kW. Recognizing extensive prior research on GaN in high-power contexts, our study initially investigates layouts, which will be used for developing optimized stackups. Our objective is, to identify stackups that maximize thermal performance while minimizing parasitic effects. The analysis establishes insulated metal substrate and copper inlay PCB stackups with vertical layouts as promising options. These results enable a flexible integration of stackup designs in high-power GaN applications and their synergy with other design objectives.
| Author of HS Reutlingen | Schullerus, Gernot; Czerwenka, Philipp; Wagenfeld, Jan Frederik |
|---|---|
| URL: | https://ieeexplore.ieee.org/document/10653872 |
| ISBN: | 978-3-8007-6262-0 |
| Published in: | PCIM Europe 2024 : International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management |
| Publisher: | VDE Verlag |
| Place of publication: | Berlin |
| Document Type: | Conference proceeding |
| Language: | English |
| Publication year: | 2024 |
| Page Number: | 8 |
| First Page: | 1134 |
| Last Page: | 1141 |
| DDC classes: | 621.3 Elektrotechnik, Elektronik |
| Open access?: | Nein |
| Licence (German): |  In Copyright - Urheberrechtlich geschützt |
