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A generic procedural generator for sizing of analog integrated circuits

  • In this paper, we address the novel EDP (Expert Design Plan) principle for procedural design automation of analog integrated circuits, which captures the knowledge-based design strategy of human circuit designers in an executable script, making it reusable. We present the EDP Player, which enables the creation and execution of EDPs for arbitrary circuits in the Cadence® Virtuoso® Design Environment. The tool provides a generic version of an instruction set, called EDPL (EDPLanguage), enabling emulation of a typical manual analog sizing flow. To automate the design of a Miller Operational Amplifier and to create variants of a Smart Power IC, several EDPs were implemented using this tool. Employing these EDPs leads to a strong reduction of design time without compromising design quality or reliability.

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Metadaten
Name:Schweikardt, Matthias; Uhlmann, Yannick; Leber, Florian; Scheible, Jürgen
DOI:https://doi.org/10.1109/PRIME.2019.8787743
ISBN:978-1-7281-3549-6
Erschienen in:PRIME 19 : 15 - 18 July, Lausanne, Switzerland : 15th Conference on PhD Research in Microelectornics and Electronics (PRIME 2019) : conference proceedings
Publisher:IEEE
Place of publication:Piscataway, NJ
Document Type:Conference Proceeding
Language:English
Year of Publication:2019
Tag:electronic design automation; expert design plan; generator; miller operational amplifier; procedure; smart power ic
Pagenumber:4
First Page:17
Last Page:20
Dewey Decimal Classification:620 Ingenieurwissenschaften und Maschinenbau
Open Access:Nein
Licence (German):License Logo  Lizenzbedingungen IEEE