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Efficiency modeling for MHz DCDC converters at 40V input voltage range

  • Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. This leads especially at a high input voltage to a decreasing efficiency caused by switching losses. Conventional calculations are not suitable to predict the efficiency as parasitic capacitances have a significant loss contribution. This paper presents an analytical efficiency model which considers parasitic capacitances separately and calculates the power loss contribution of each capacitance to any resistive element. The proposed model is utilized for efficiency optimization of converters with switching frequencies >10MHz and input voltages up to 40V. For experimental evaluation a DCDC converter was manufactured in a 180 nm HV BiCMOS technology. The model matches a transistor level simulation and measurement results with an accuracy better than 3.5 %. The accuracy of the parasitic capacitances of the high voltage transistor determines the overall accuracy of the efficiency model. Experimental capacitor measurements can be fed into the model. Based on the model, different architectures have been studied.

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Author of HS ReutlingenWittmann, Jürgen; Wicht, Bernhard
Erschienen in:Advances in radio science : Kleinheubacher Berichte
Place of publication:Darmstadt
Document Type:Journal article
Publication year:2014
Page Number:6
First Page:111
Last Page:115
DDC classes:550 Geowissenschaften
620 Ingenieurwissenschaften und Maschinenbau
Open access?:Ja
Licence (German):License Logo  Creative Commons - Namensnennung