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CAPABLE : a layout automation framework for analog IC design

  • In practice, the use of layout PCells for analog IC design has not advanced beyond primitive devices and simple modules. This paper introduces a Constraint-Administered PCell-Applying Blocklevel Layout Engine (CAPABLE) which permits PCells to access their context, thus enabling a true "bottom-up" development of complex parameterized modules. These modules are integrated into the design flow with design constraints and applied by an execution cockpit via an automatically built layout script. The practical purpose of CAPABLE is to easily generate full-custom block layouts for given schematic circuits. Perspectively, our results inspire a whole new conception of PCells that can not only act (on demand), but also react (to environmental changes) and interact (with each other).

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Author of HS ReutlingenMarolt, Daniel; Scheible, Jürgen
Publisher:Hochschule Ulm
Place of publication:Ulm
Editor:Gerhard Forster
Document Type:Conference proceeding
Publication year:2015
Tag:analog IC design; bottom- up design; design constraints; layout automation; parameterized cells
Page Number:11
First Page:49
Last Page:59
DDC classes:621 Angewandte Physik
Open access?:Ja
Licence (German):License Logo  Open Access