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Substrate coupling in fast-switching integrated power stages

  • Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.

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Author of HS ReutlingenWittmann, Jürgen; Rindfleisch, Christoph; Wicht, Bernhard
Erschienen in:2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) ; date: 10 - 14 May 2015
Place of publication:Piscataway, NJ
Editor:Johnny Sin
Document Type:Conference proceeding
Publication year:2015
Page Number:4
First Page:341
Last Page:344
DDC classes:621 Angewandte Physik
Open access?:Nein
Licence (German):License Logo  In Copyright - Urheberrechtlich geschützt