Formal verification of a transistor PCell
- Layout generators, commonly denoted as PCells (parameterized cells), play an important role in the layout design of analog ICs (integrated circuits). PCells can automatically create parts of a layout, whose properties are controlled by the PCell parameters. Any layout, whether hand-crafted or automatically generated, has to be verified against design rules using a DRC (design rule check) in order to assure proper functionality and producibility. Due to the growing complexity of today’s PCells it would be beneficial if a PCell itself could be ensured to produce DRC clean layouts for any allowed parameter values, i.e. a formal verification of the PCell’s code rather than checking all possible instances of the PCell. In this paper we demonstrate the feasibility of such a formal PCell verification for a simple NMOS transistor PCell. The set from which the parameter values can be chosen was found during the verification process.
| Author of HS Reutlingen | Scheible, Jürgen; Langner, Kerstin |
|---|---|
| DOI: | https://doi.org/10.1109/PRIME.2017.7974143 |
| ISBN: | 978-1-5090-6508-0 |
| Erschienen in: | PRIME 2017 : 13th Conference on PH.D. Research in Microelectronics and Eletronics : conference proceedings : 12th-15th June 2017, Giardini Naxos, Taormina, Italy |
| Publisher: | IEEE |
| Place of publication: | Piscataway, NJ |
| Editor: | Salvatore Pennisi |
| Document Type: | Conference proceeding |
| Language: | English |
| Publication year: | 2017 |
| Tag: | DRC compliance; PCell; formal verification; layout generator |
| Page Number: | 4 |
| First Page: | 205 |
| Last Page: | 208 |
| DDC classes: | 620 Ingenieurwissenschaften und Maschinenbau |
| Open access?: | Nein |
| Licence (German): |  In Copyright - Urheberrechtlich geschützt |
