Volltext-Downloads (blau) und Frontdoor-Views (grau)

A hysteretic buck converter with 92.1% maximum efficiency designed for ultra-low power and fast wake-up SoC applications

  • This paper presents a dc–dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc–dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130 nm CMOS technology with an area of only 0.14 mm². It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.

Download full text files

  • 2102.pdf

Export metadata

Additional Services

Share in Twitter Search Google Scholar


Author of HS ReutlingenWicht, Bernhard
Erschienen in:IEEE journal of solid state circuits
Publisher:New York, NY
Place of publication:IEEE
Document Type:Article
Year of Publication:2018
Tag:buck; dc–dc; fast wake-up; low energy; low power; minimized capacitor; wake-up energy
Page Number:13
First Page:1856
Last Page:1868
DDC classes:620 Ingenieurwissenschaften und Maschinenbau
Open Access?:Nein
Licence (German):License Logo  Lizenzbedingungen IEEE