A 50V, 1.45ns, 4.1pJ high-speed low-power level sifter for high-voltage DCDC converters
- The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high speed and power-efficient level shifter for voltages of up to 50V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv / dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40% compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180nm BiCMOS technology. Measurements confirm a 50V 120MHz high-speed operation of the level shifter with a rising / falling propagation delay of 1.45 ns / 1.3 ns, respectively. The dv / dt robustness has been confirmed by measurements for transitions up to 6V/ ns.
| Author of HS Reutlingen | Lutz, Daniel; Seidel, Achim; Wicht, Bernhard |
|---|---|
| DOI: | https://doi.org/10.1109/ESSCIRC.2018.8494292 |
| ISBN: | 978-1-5386-5404-0 |
| Erschienen in: | ESSCIRC 2018 : IEEEE 44th European Solid State Circuits Conference (ESSCIRC) : 3-6 Sept. 2018 |
| Publisher: | IEEE |
| Place of publication: | Piscataway, NJ |
| Document Type: | Conference Proceeding |
| Language: | English |
| Year of Publication: | 2018 |
| Tag: | DCDC power converter; high-speed; high-voltage level shifter; low power |
| Page Number: | 4 |
| First Page: | 126 |
| Last Page: | 129 |
| DDC classes: | 620 Ingenieurwissenschaften und Maschinenbau |
| Open Access?: | Nein |
| Licence (German): |  Lizenzbedingungen IEEE |
