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Active time-constant error compensation in multi-bit continuous-time delta-sigma modulators

  • We present a technique to compensate the effects of process variation induced R-C / gm−C time-constant (TC) errors in continuous-time (CT) delta-sigma modulators with multibit quantizers. Tunable error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with actively tunable circuit structures, such as the digital-to-analog converters in the feedback paths. This work constitutes a generalization of our previously published TC error compensation technique, which only considered modulators with single-bit quantizers. In the multi-bit case, special attention must be paid to the adjustment of the effective quantizer gain as a function of TC errors on the system and the circuit levels. We derive an active TC tuning scheme for multi-bit CT delta-sigma modulators in cascaded integrator feedback structure. The tuning scheme is applied to a 3-bit modulator circuit implemented in a 0.35−μm CMOS process. Corner simulations on the transistor level confirm constant nominal performance and stable operation across TC variation of ±30%.

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Metadaten
Author of HS ReutlingenHennig, Eckhard; Wolfer, Tobias
DOI:https://doi.org/10.1109/APCCAS67402.2025.11377347
ISBN:979-8-3315-8907-3
Published in:2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ; 12-15 October 2025, Busan, Korea
Publisher:IEEE
Place of publication:Piscataway
Document Type:Conference proceeding
Language:English
Publication year:2025
Tag:CMOS process; circuits and systems; delta-sigma modulation; digital-analog conversion; error compensation; integrated circuit modeling; modulation; semiconductor device modeling; transistors; tuning
Page Number:5
DDC classes:600 Technik
Open access?:Nein
Licence (German):License Logo  In Copyright - Urheberrechtlich geschützt