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The 17 SDGs, as agreed upon by the international community, are designed to be implemented across all levels of human activity. Alongside the level of international politics, this also includes the local levels, national politics, wider society, and the economic sphere. Many channels are called on to further implementation, including the transfer of technology to developing and emerging countries. As the patent holders, this must include the active participation of companies. While the literature examines the important role of technology transfer in North-South business-to-business (B2B) partnerships, studies on the technology transfer between European and African companies are scarce. Therefore, in this study we use original data from 26 interviews conducted with managers engaged in sales partnerships between German manufacturers and their distributors in African markets to examine the existence and forms of technology transfer. We find that training and marketing excellence are the predominant forms of technology transfer and based on that suggest a refinement of established frameworks on B2B technology transfer.
Excellence in IT is both a driver and a key enabler of the digital transformation. The digital transformation changes the way we live, work, learn, communicate, and collaborate. The Internet of Things (IoT) fundamentally influences today’s digital strategies with disruptive business operating models and fast changing markets. New business information systems are integrating emerging Internet of Things infrastructures and components. With the huge diversity of Internet of Things technologies and products organizations have to leverage and extend previous Enterprise Architecture efforts to enable business value by integrating Internet of Things architectures. Both architecture engineering and management of current information systems and business models are complex and currently integrating beside the Internet of Things synergistic subjects, like Enterprise Architecture in context with services & cloud computing, semantic-based decision support through ontologies and knowledge-based systems, big data management, as well as mobility and collaboration networks. To provide adequate decision support for complex business/IT environments, we have to make transparent the impact of business and IT changes over the integral landscape of affected architectural capabilities, like directly and transitively impacted IoT-objects, business categories, processes, applications, services, platforms and infrastructures. The paper describes a new metamodel-based approach for integrating Internet of Things architectural objects, which are semi-automatically federated into a holistic Digital Enterprise Architecture environment.
Digitization fosters the development of IT environments with many rather small structures, like Internet of Things (IoT), microservices, or mobility systems. They are needed to support flexible and agile digitized products and services. The goal is to create service-oriented enterprise architectures (EA) that are self optimizing and resilient. The present research paper investigates methods for decision-making concerning digitization architectures for Internet of Things and microservices. They are based on evolving enterprise architecture reference models and state of the art elements for architectural engineering for microgranular systems. Decision analytics in this field becomes increasingly complex and decision support, particularly for the development and evolution of sustainable enterprise architectures, is sorely needed. The challenging of the decision processes can be supported with in a more flexible and intuitive way by an architecture management cockpit.
The digital transformation of our life changes the way we work, learn, communicate, and collaborate. Enterprises are presently transforming their strategy, culture, processes, and their information systems to become digital. The digital transformation deeply disrupts existing enterprises and economies. Digitization fosters the development of IT systems with many rather small and distributed structures, like Internet of Things, Microservices and mobile services. Since years a lot of new business opportunities appear using the potential of services computing, Internet of Things, mobile systems, big data with analytics, cloud computing, collaboration networks, and decision support. Biological metaphors of living and adaptable ecosystems provide the logical foundation for self optimizing and resilient run-time environments for intelligent business services and adaptable distributed information systems with service oriented enterprise architectures. This has a strong impact for architecting digital services and products following both a value-oriented and a service perspective. The change from a closed world modeling world to a more flexible open-world composition and evolution of enterprise architectures defines the moving context for adaptable and high distributed systems, which are essential to enable the digital transformation. The present research paper investigates the evolution of Enterprise Architecture considering new defined value-oriented mappings between digital strategies, digital business models and an improved digital enterprise architecture.
The internet of things, enterprise social networks, adaptive case management, mobility systems, analytics for big data, and cloud environments are emerging to support smart connected i.e. digital products and services and the digital transformation. Biological metaphors for living and adaptable ecosystems are currently providing the logical foundation for resilient run-time environments with serviceoriented digitization architectures and for self-optimizing intelligent business services and related distributed information systems. We are investigating mechanisms for flexible adaptation and evolution of information systems with digital architecture in the context of the ongoing digital transformation. The goal is to support flexible and agile transformations for both business and related information systems through adaptation and dynamical evolution of their digital architectures. The present research paper investigates mechanisms of decision analytics for digitization architectures, putting a spotlight to internet of things micro-granular architectures, by extending original enterprise architecture reference models with digitization architectures and their multi-perspective architectural decision management.
SmartLife ecosystems are emerging as intelligent user-centered systems that will shape future trends in technology and communication. Biological metaphors of living adaptable ecosystems provide the logical foundation for self-optimizing and self-healing run-time environments for intelligent adaptable business services and related information systems with service-oriented enterprise architectures. The present research in progress work investigates mechanisms for adaptable enterprise architectures for the development of service-oriented ecosystems with integrated technologies like Semantic Technologies, Web Services, Cloud Computing and Big Data Management. With a large and diverse set of ecosystem services with different owners, our scenario of service-based SmartLife ecosystems can pose challenges in their development, and more importantly, for maintenance and software evolution. Our research explores the use of knowledge modeling using ontologies and flexible metamodels for adaptable enterprise architectures to support program comprehension for software engineers during maintenance and evolution tasks of service-based applications. Our previous reference enterprise architecture model ESARC -- Enterprise Services Architecture Reference Cube -- and the Open Group SOA Ontology was extended to support agile semantic analysis, program comprehension and software evolution for a SmartLife applications scenario. The Semantic Browser is a semantic search tool that was developed to provide knowledge-enhanced investigation capabilities for service-oriented applications and their architectures.
This paper presents a permanent magnet tubular linear generator system for powering passive sensors using vertical vibration harvesting energy. The system consists of a permanent magnet tubular linear vibration generator and electric circuits. By using the design of mechanical resonant movers, the generator is capable of converting low frequencies small amplitude vertical vibration energy into more regular sinusoidal electrical energy. The distribution of the magnetic field and electromotive force are calculated by Finite Element Analysis. The characteristics of the linear vibration generator system are observed. The experimental results show the generator can produce about 0.4W~1.6W electrical power when the vibration source's amplitude is fixed on 2mm and the frequencies are between 13Hz and 22Hz.
Accurate and safe neurosurgical intervention can be affected by intra-operative tissue deformation, known as brain-shift. In this study, we propose an automatic, fast, and accurate deformable method, called iRegNet, for registering pre-operative magnetic resonance images to intra-operative ultrasound volumes to compensate for brain-shift. iRegNet is a robust end-to-end deep learning approach for the non-linear registration of MRI-iUS images in the context of image-guided neurosurgery. Pre-operative MRI (as moving image) and iUS (as fixed image) are first appended to our convolutional neural network, after which a non-rigid transformation field is estimated. The MRI image is then transformed using the output displacement field to the iUS coordinate system. Extensive experiments have been conducted on two multi-location databases, which are the BITE and the RESECT. Quantitatively, iRegNet reduced the mean landmark errors from pre-registration value of (4.18 ± 1.84 and 5.35 ± 4.19 mm) to the lowest value of (1.47 ± 0.61 and 0.84 ± 0.16 mm) for the BITE and RESECT datasets, respectively. Additional qualitative validation of this study was conducted by two expert neurosurgeons through overlaying MRI-iUS pairs before and after the deformable registration. Experimental findings show that our proposed iRegNet is fast and achieves state-of-the-art accuracies outperforming state-of-the-art approaches. Furthermore, the proposed iRegNet can deliver competitive results, even in the case of non-trained images as proof of its generality and can therefore be valuable in intra-operative neurosurgical guidance.
DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.
DMOS transistors often suffer from substantial self-heating during high power dissipation, which can lead to thermal destruction if the device temperature reaches excessive values. A successfully demonstrated method to reduce the peak temperature is the redistribution of power dissipation density from the hotter to the cooler device areas by careful layout modification. However, this is very tedious and time-consuming if complex-shaped devices as often found in industrial applications are considered.
This paper presents an approach for fully automatic layout optimization which requires only a few hours processing time. The approach is applied to complex shaped test structures which are investigated by measurements and electro-thermal simulations. Results show a significantly lower peak temperature and an energy capability gain of 84 %, offering potential for a 18 % size reduction of active area.
In this paper, it aims to model wind speed time series at multiple sites. The five-parameter Johnson distribution is deployed to relate the wind speed at each site to a Gaussian time series, and the resultant m-dimensional Gaussian stochastic vector process Z(t) is employed to model the temporal-spatial correlation of wind speeds at m different sites. In general, it is computationally tedious to obtain the autocorrelation functions (ACFs) and cross-correlation functions (CCFs) of Z(t), which are different to those of wind speed times series. In order to circumvent this correlation distortion problem, the rank ACF and rank CCF are introduced to characterize the temporal-spatial correlation of wind speeds, whereby the ACFs and CCFs of Z(t) can be analytically obtained. Then, Fourier transformation is implemented to establish the cross-spectral density matrix of Z(t), and an analytical approach is proposed to generate samples of wind speeds at m different sites. Finally, simulation experiments are performed to check the proposed methods, and the results verify that the five-parameter Johnson distribution can accurately match distribution functions of wind speeds, and the spectral representation method can well reproduce the temporal-spatial correlation of wind speeds.
Continuous refactoring is necessary to maintain source code quality and to cope with technical debt. Since manual refactoring is inefficient and error prone, various solutions for automated refactoring have been proposed in the past. However, empirical studies have shown that these solutions are not widely accepted by software developers and most refactorings are still performed manually. For example, developers reported that refactoring tools should support functionality for reviewing changes. They also criticized that introducing such tools would require substantial effort for configuration and integration into the current development environment.
In this paper, we present our work towards the Refactoring-Bot, an autonomous bot that integrates into the team like a human developer via the existing version control platform. The bot automatically performs refactorings to resolve code smells and presents the changes to a developer for asynchronous review via pull requests. This way, developers are not interrupted in their workflow and can review the changes at any time with familiar tools. Proposed refactorings can then be integrated into the code base via the push of a button. We elaborate on our vision, discuss design decisions, describe the current state of development, and give an outlook on planned development and research activities.
Verification of an active time constant tuning technique for continuous-time delta-sigma modulators
(2022)
In this work we present a technique to compensate the effects of R-C / g m -C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with finely tunable circuit structures, such as current-steering digital-to-analog converters (DAC). We apply our technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure, implemented in a 0.35-μm CMOS process. A tuning scheme for the reference currents of the feedback DACs is derived as a function of the individual TC errors and verified by circuit simulations. We confirm the tuning technique experimentally on the fabricated circuit over a TC parameter variation range of ±20%. Stable modulator operation is achieved for all parameter sets. The measured performances satisfy the expectations from our theoretical calculations and circuit-level simulations.
We present the results of an extensive characterization of the performance and stability of a third-order continuous-time delta-sigma modulator with active coefficient error compensation. Using our previously published coefficient tuning technique, process variation induced R-C time-constant (TC) errors in the forward signal path can be compensated indirectly using continuously tunable DACs in the feedback path. To validate our technique experimentally with a range of real TC variations, we designed a modulator with discretely configurable integration capacitor arrays in a 0.35-μm CMOS process. We configured the capacitors of the fabricated device for a range of total TC variations from -28.4 % to +19.3 % and measured the signal-to-noise ratio (SNR) as a function of the input amplitude before and after compensating the variations electrically using the feedback DACs. The results show that our tuning technique is capable of restoring the desired nominal modulator performance over the entire parameter variation range, including the system’s nominal maximum stable amplitude (MSA).
We propose a novel technique to compensate the effects of R-C / gm-C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with tunable circuit structures, such as current-steering digital-to-analog converters (DAC). This approach constitutes an alternative or supplement to existing compensation techniques, including capacitor or gm tuning. We apply the proposed technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure. A feedback path tuning scheme is derived analytically and confirmed numerically using behavioral simulations. The modulator circuit was implemented in a 0.35-μm CMOS process using an active feedback coefficient tuning structure based on current-steering DACs. Post-layout simulations show that with this tuning structure, constant performance and stable operation can be obtained over a wide range of TC variation.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum conversion ratio are limited by the duty cycle of a PWM signal. In DCDC converters, a sawtooth generator is the fundamental circuit block to generate the PWM signal. The presented PWM generator is based on two parallel, fully interleaved PWM generator stages, each containing an integrator based sawtooth generator and two 3-stage highspeed comparators. A digital multiplexing of the PWM signals of each stage eliminates the dependency of the minimum on-time on the large reset times of the sawtooth ramps. A separation of the references of the PWM comparators in both stage allows to configure the PWM generator for a DCDC converter operating in fixed frequency or in constant on-time mode, which requires an operation in a wide frequency range. The PWM generator was fabricated in an 180 nm HV BiCMOS technology, as part of a DCDC converter. Measurements confirm minimum possible ontime pulses as short as 2 ns and thus allows switching frequencies of DCDC converters of >50 MHz at small duty cycle of <10%. At moderate duty cycles switching frequencies up to 100 MHz are possible.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
The presented wide-Vin step-down converter introduces a parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300 nH resonant coil, placed in parallel to a conventional buck converter. Unlike conventional resonant concepts, the implemented soft-switching control eliminates input voltage dependent losses over a wide operating range. This ensures high efficiency across a wide range of Vin= 12-48V, 100-500mA load and 5V output at up to 15MHz switching frequency. The peak efficiency of the converter is 76.3 %. Thanks to the low output current ripple, the output capacitor can be as small as 50 nF, while the inductor tolerates a larger ESR, resulting in small component size. The proposed PRC architecture is also suitable for future power electronics applications using fast-switching GaN devices.
This paper presents a wide-Vin step-down parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300-nH resonant coil, placed in parallel to a conventional buck converter. Soft-switching resonant converters are beneficial for high-Vin multi-MHz converters to reduce dominant switching losses, enabling higher switching frequencies. The output filter inductor is optimized based on an empirical study of available inductors. The study shows that faster switching significantly reduces not only the inductor value but also volume, price, and even the inductor losses. In addition, unlike conventional resonant concepts, soft-switching control as part of the proposed PRC eliminates input voltage-dependent losses over a wide operating range, resulting in 76.3% peak efficiency. At Vin = 48 V, a loss reduction of 35% is achieved compared with the conventional buck converter. Adjusting an integrated capacitor array, and selecting the number of oscillation periods, keeps the switching frequency within a narrow range. This ensures high efficiency across a wide range of Vin = 12–48 V, 100–500-mA load, and 5-V output at up to 25-MHz switching frequency. Thanks to the low output current ripple, the output capacitor can be as small
as 50 nF.