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This work investigates the electro-thermal behavior and failure mechanism of a 600V depletion-mode GaN HEMT by experimental analysis and numerical thermal simulations. For this device, the positive temperature coefficient of the draingate leakage current can lead to the formation of hot spots. This localized thermal runaway which ultimately results in a breakdown of the inherent drain-gate junction is found to be the dominant cause of failure.
Die vorliegende Erfindung betrifft ein Transmission Line Pulssystem zum Erzeugen eines elektrischen Pulses, sowie ein diesbezügliches Verfahren. Dabei umfasst das Transmission Line Pulssystem: eine Transmission Line, eine Energieversorgungsquelle zum Aufladen der Transmission Line und einen Entladungsschalter zum Auslösen einer Entladung der aufgeladenen Transmission Line, dadurch gekennzeichnet, dass die Transmission Line eine Vielzahl von Einzelsegmenten umfasst, wobei jedes Einzelsegment über ein zugehöriges Einstellglied mit einem gemeinsamen Massepotential elektrisch verbunden ist, und wobei zumindest eines der Einstellglieder einen Einstellkondensator und einen Einstellschalter aufweist.
An experimental study of a zero voltage switching SiC boost converter with an active snubber network
(2015)
This paper presents a quasi-resonant, zero voltage switching (ZVS) SiC boost converter for an output power of up to 10 kW. The converter is realized with an easily controllable active snubber network that allows a reduction of switching losses by minimizing the voltage stress applied to the active switch. With this approach, an increase of the switching frequency is possible, allowing a reduction of the system size. Experiments show a maximum converter efficiency up to 99.2% for a switching frequency of 100 kHz. A second version of the converter enables a further size reduction by increasing the switching frequency to 300 kHz while still reaching a high efficiency up to 98.4 %.
DMOS transistors in integrated smart power technologies are often subject to cyclic power dissipation with substantial selfheating. This leads to repetitive thermo mechanical stress, causing fatigue of the on-chip metallization and limiting the lifetime. Hence, most designs use large devices for lower peak temperatures and thus reduced stress to avoid premature failures.
However, significantly smaller DMOS transistors are acceptable if the system reverts to a safer operating condition with lower stress when a failure is expected to occur in the near future. Hence, suitable early-warning sensors are required. This paper proposes a floating metal meander embedded between DMOS source and drain to detect an impending metallization failure. Measurement results of several variants will be presented and discussed, investigating their suitability as early warning indicators.
Large power semiconductors are complex structures, their metallization usually containing many thousands of contacts or vias. Because of this, detailed FEM simulations of the whole device are nowadays not possible because of excessive simulation time.
This paper introduces a simulation approach which allows quick identification of critical regions with respect to lifetime by a simplified simulation. For this, the complex layers are replaced by a much simpler equivalent layer, allowing a simulation of the whole device even including its package. In a second step, precise simulations taking all details of the structure into account are carried out, but only for the critical regions of interest. Thus, this approach gives detailed results where required with consideration of the whole structure including packaging. Further, the simulation time requirements are very moderate.
The experimental characterization of the thermal impedance Zth of large power MOSFETs is commonly done by measuring the junction temperature Tj in the cooling phase after the device has been heated, preferably to a high junction temperature for increased accuracy. However, turning off a large heating current (as required by modern MOSFETs with low on-state resistances) takes some time because of parasitic inductances in the measurement system. Thus, most setups do not allow the characterization of the junction temperature in the time range below several tens of μs.
In this paper, an optimized measurement setup is presented which allows accurate Tj characterization already 3 μs after turn-off of heating. With this, it becomes possible to experimentally investigate the influence of thermal capacitances close to the active region of the device. Measurement results will be presented for advanced power MOSFETs with very large heating currents up to 220 A. Three bonding variants are investigated and the observed differences will be explained.
A TLP system with a very low characteristic impedance of 1.5 Ω and a selectable pulse length from 0.5 to 6 μs is presented. It covers the entire operation region of many power semiconductors up to 700 V and 400 A. Ist applicability is demonstrated by determining the Output characteristics for two Cool MOS devices up to destruction.
This paper presents a measurement setup and an assembly technique suitable for characterization of power semiconductor devices under very high temperature conditions exceeding 500°C. An important application of this is the experimental investigation of wide bandgap semiconductors. Measurement results are shown for a 1200V SiC MOSFET and a 650V depletion mode GaN HEMT.
DMOS transistors often suffer from substantial self-heating during high power dissipation, which can lead to thermal destruction if the device temperature reaches excessive values. A successfully demonstrated method to reduce the peak temperature is the redistribution of power dissipation density from the hotter to the cooler device areas by careful layout modification. However, this is very tedious and time-consuming if complex-shaped devices as often found in industrial applications are considered.
This paper presents an approach for fully automatic layout optimization which requires only a few hours processing time. The approach is applied to complex shaped test structures which are investigated by measurements and electro-thermal simulations. Results show a significantly lower peak temperature and an energy capability gain of 84 %, offering potential for a 18 % size reduction of active area.
Modern power DMOS transistors greatly benefit from the continuous advances of the technology, which yield devices with very low area-specific RDS,on figures of merit and therefore allow for significantly reduced active areas. However, in many applications, where the devices must dissipate high amounts of energy and thus are subjected to significant self-heating, the active area is not dictated by RDS,on requirements, but by the energy constraints. In this paper, a simple method of improving the energy capability and reliability of power DMOS transistors operating in pulsed conditions is proposed and experimentally verified. The method consists in redistributing the power density from the hotter to the cooler device regions, hence achieving a more homogeneous temperature distribution and a reduced peak temperature. To demonstrate the principle, a simple gate offset circuit is used to redistribute the current density to the cooler DMOS parts. No technology changes are needed for the implementation, only minor changes to the driver circuit are necessary, with a minimal impact on the additional required active area. Improvements in the energy capability from 9.2% up to 39% have been measured. Furthermore, measurements have shown that the method remains effective also if the operating conditions change significantly. The simplicity and the effectiveness of the implementation makes the proposed method suitable to be used in a wide range of applications.