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Novel design for a coreless printed circuit board transformer realizing high bandwidth and coupling
(2019)
Rogowski coils offer galvanic isolation and can measure alternating currents with a high bandwidth. Coreless printed circuit board (PCB) transformers have been used as an alternative to limit the additional stray inductance if a Rogowski coil can not be attached to the circuit. A new PCB transformer layout is proposed to reduce cost, decrease additional stray inductance, increase the bandwidth of current measurements and simplify the integration into existing designs.
Many GaN power transistors contain a PN junction between gate and the channel region close to the source. In order to maintain the on-state, current must continuously be supplied to the junction. Therefore, the commonly recommended approach uses a gate bias voltage of 12V to compensate the Miller current through a boost circuit. For the same purpose, a novel gate driving method based on an inductive feed forward has been presented. With this, stable turn-on can be achieved even for a bias voltage of only 5V. The effectiveness of this concept is demonstrated by double pulse measurements, switching currents up to 27A and a voltage of 400V. For both approaches a compact design with low source inductance is characterized. In addition to the significant reduction of the gate bias voltage and peak gate current, the new approach reduces the switching losses for load currents >23 A.
We present a dual active bridge topology suitable for wide voltage range applications covering all combinations of 200V to 600V on the input and 20V to 60V on the output with constant power of 1kW.We employ a stepped inductance scheme to adjust the effective inductance of the converter, thus extending the efficient operation range. Using a variable switching frequency between 35 kHz and 150 kHz with operation-point-dependent limits further increases the performance of the converter. A prototype was built and the proposed changes have been compared to a fixed frequency, fixed inductance implementation. Measurements show a maximum loss reduction of 40 %, leading to a peak efficiency of 97% while maintaining constant output power over the entire working area.
A novel gate driving approach to balance the transient current of parallel-connected GaN-HEMTs
(2018)
To enable higher current handling capability of GaN-based DC/DC converters, devices have to be used in parallel. However, their switching times differ, especially if their threshold voltages are not identical, which causes unbalanced device current. This paper focuses on the homogeneous distribution of turn-on switching losses of GaN-HEMTs connected in parallel. By applying a new gate driver concept, the transient current is distributed evenly. The effectiveness of this concept is demonstrated by double pulse measurements, for switching currents up to 45A and a voltage of 400V. A uniform current distribution is achieved, including a reduction of the turn-on losses by 50% compared to a conventional setup.
Gallium nitride high electron mobility transistors (GaN-HEMTs) have low capacitances and can achieve low switching losses in applications where hard turn-on is required. Low switching losses imply a fast switching; consequently, fast voltage and current transients occur. However, these transients can be limited by package and layout parasitics even for highly optimized systems. Furthermore, a fast switching requires a fast charging of the input capacitance, hence a high gate current.
In this paper, the switching speed limitations of GaN-HEMTs due to the common source inductance and the gate driver supply voltage are discussed. The turn-on behavior of a GaN-HEMT is simulated and the impact of the parasitics and the gate driver supply voltage on the switching losses is described in detail. Furthermore, measurements are performed with an optimized layout for a drain-source voltage of 500 V and a drain-source current up to 60 A.
Modern power semiconductor devices have low capacitances and can therefore achieve very fast switching transients under hard-switching conditions. However, these transients are often limited by parasitic elements, especially by the source inductance and the parasitic capacitances of the power semiconductor. These limitations cannot be compensated by conventional gate drivers. To overcome this, a novel gate driver approach for power semiconductors was developed. It uses a transformer which accelerates the switching by transferring energy from the source path to the gate path.
Experimental results of the novel gate driver approach show a turn-on energy reduction of 78% (from 80 μJ down to 17 μJ) with a drain-source voltage of 500V and a drain current of 60 A. Furthermore, the efficiency improvement is demonstrated for a hard-switching boost converter. For a switching frequency of 750 kHz with an input voltage of 230V and an output voltage of 400V, it was possible to extend the output power range by 35%(from 2.3kW to 3.1 kW), due to the reduction of the turn-on losses, therefore lowering the junction temperature of the GaN-HEMT.
A gate driver approach is presented for the reduction of turn-on losses in hard switching applications. A significant turn-on loss reduction of up to 55% has been observed for SiCMOSFETs. The gate driver approach uses a transformer which couples energy from the power path back into the gate path during switching events, providing increased gate driver current and thereby faster switching speed.
The gate driver approach was tested on a boost converter running at a switching frequency up to 300 kHz. With an input voltage of 300V and an output voltage of 600V, it was possible to reduce the converter losses by 8% at full load. Moreover, the output power range could be extended by 23% (from 2.75kW to 3.4 kW) due to the reduction of the turn-on losses.
In this work we investigate the behavior of MIS- and Schottky-gate AlGaN/GaN HEMTs under high-power pulsestress. A special setup capable of applying pulses of constant power is used to evaluate the electro-thermal response in different operating points. For both types of devices, the time to failure was found to decrease with increasing drain-source voltage. Overall, the Schottky-gate device displays a higher pulse robustness. The pulse withstand time of the MIS-gate device is limited by the occurrence of a thermal instability at approximately 240°C while the Schottky-gate device displays a rapid increase of the gate leakage current prior to failure. The mechanism responsible for this gate current is further investigated by static and transient temperature measurements and yielded activation energies of 0.6 eV and 0.84 eV.
LDMOS transistors in integrated power technologies are often subject to thermo-mechanical stress, which degrades the on-chip metallization and eventually leads to a short. This paper investigates small sense lines embedded in the LDMOS metallization. It will be shown that their resistance depends strongly on the stress cycle number. Thus, they can be used as aging sensors and predict impending failures. Different test structures have been investigated to identify promising layout configurations. Such sensors are key components for resilient systems that adaptively reduce stress to allow aggressive LDMOS scaling without increasing the risk of failure.
A novel configuration of the dual active bridge (DAB) DC/DC converter is presented, enabling more efficient wide voltage range conversion at light loads. A third phase leg as well as a center tapped transformer are introduced to one side of the converter. This concept provides two different turn ratios, thus extending the zero voltage switching operation resulting in higher efficiency. A laboratory prototype was built converting an input voltage of 40V to an output voltage in the range of 350V to 650V. Measurements show a significant increase up to 20% in the efficiency for light-load operation.