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Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
Durch schnell schaltende Leistungsendstufen werden durch kapazitive Umladeströme Störungen ins Substrat und in empfindliche Schaltungselemente eingekoppelt, die dort zur Störung der Funktion führen können. In dieser Arbeit werden Substratstrukturen zur gezielten Ableitung dieser Störungen vorgestellt und ihre Wirksamkeit mit Hilfe von Device Simulation evaluiert. Ohne Ableitstrukturen kann eine Potentialanhebung des Substrats bis zu 20 V entstehen. Die Untersuchungen belegen, dass die Potentialanhebung durch p-Typ Guard-Ringe um 75 %, durch leitende Trenches um 88 % sowie durch Rückseitenmetallisierung um nahezu 100 % reduziert werden kann.
The efficiency impact of air-cored inductors used close to and beyond its cut-off frequency in multi-MHz converters is investigated. A method is presented to determine the converter switching frequency that causes the lowest losses in a given inductor. Influential parameters are analysed to optimize an inductor for a predefined switching frequency.