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This paper presents a machine learning powered, procedural sizing methodology based on pre-computed look-up tables containing operating point characteristics of primitive devices. Several Neural Networks are trained for 90nm and 45nm technologies, mapping different electrical parameters to the corresponding dimensions of a primitive device. This transforms the geometric sizing problem into the domain of circuit design experts, where the desired electrical characteristics are now inputs to the model. Analog building blocks or entire circuits are expressed as a sequence of model evaluations, capturing the sizing strategy and intention of the designer in a procedure, which is reusable across different technology nodes. The methodology is employed for the sizing of two operational amplifiers, and evaluated for two technology nodes, showing the versatility and efficiency of this approach.
This paper presents an improvement in usability and integrity of simulation-based analog circuit sizing. Instead of using geometrical sizing parameters (width, length), a transformed design-space, consisting exclusively of electrical parameters (branch currents, efficiencies and speed) is utilized. This design-space is explored more efficiently by optimizers. Moreover, this design-space can be reduced without affecting the quality of the result. The method is illustrated on two application examples, a symmetrical and a miller operational amplifier. Sizing the circuits using the transformed design-space showed significant reduction in required circuit simulations (up to 11x faster), better convergence, without loss in quality.
Electronic design automation approaches can roughly be divided into optimizers and procedures. While the former have enabled highly automated synthesis flows for digital integrated circuits, the latter play a vital (but mostly underestimated role) in the analog domain. This paper describes both automation strategies in comparison, identifying two fundamentally different automation paradigms that reflect the two basic design practices known as “top-down” and “bottom-up”. Then, with a focus on the latter, the history of procedural approaches is traced from their
early beginnings until today’s evolvements and future prospects to underline their practical importance and to accentuate their scientific value, both in itself and in the overall context of EDA.
Dieses Buch vermittelt die grundlegenden Kenntnisse für den Layoutentwurf digitaler und analoger Schaltungen. Neben den ingenieurwissenschaftlichen Grundlagen werden auch Werkzeugaspekte behandelt. Das Werk befähigt Ingenieure, einen Schaltplan oder eine Netzliste in eine Layoutdarstellung zur Fertigung eines integrierten Schaltkreises (IC) oder einer Leiterplatte umzusetzen. Nach einer einleitenden Übersicht zu Fertigungstechnologien, Besonderheiten der Mikroelektronik und den Aufgaben des Layoutentwurfs behandelt Kap. 2 zunächst die technologischen Grundlagen der IC-Fertigung. Darauf aufbauend werden nachfolgend alle Aspekte des Layoutentwurfs vertieft: Schnittstellen, Entwurfsregeln und Bibliotheken (Kap. 3), Entwurfsstile, -modelle und -flüsse (Kap. 4), Entwurfsschritte (Kap. 5), Besonderheiten des analogen IC-Entwurfs (Kap. 6) und schließlich Zuverlässigkeitsmaßnahmen (Kap. 7). Das Buch eignet sich als Lehrbuch in den Ingenieurwissenschaften und als Nachschlagewerk für Schaltungs- und Layoutentwickler in der Industrie.
Analog integrated circuit sizing is notoriously difficult to automate due to its complexity and scale; thus, it continues to heavily rely on human expert knowledge. This work presents a machine learning-based design automation methodology comprising pre-defined building blocks such as current mirrors or differential pairs and pre-computed look-up tables for electrical characteristics of primitive devices. Modeling the behavior of primitive devices around the operating point with neural networks combines the speed of equation-based methods with the accuracy of simulation-based approaches and, thereby, brings quality of life improvements for analog circuit designers using the gm/Id method. Extending this procedural automation method for human design experts, we present a fully autonomous sizing approach. Related work shows that the convergence properties of conventional optimization approaches improve significantly when acting in the electrical domain instead of the geometrical domain. We, therefore, formulate the circuit sizing task as a sequential decision-making problem in the alternative electrical design space. Our automation approach is based entirely on reinforcement learning, whereby abstract agents learn efficient design space navigation through interaction and without expert guidance. These agents’ learning behavior and performance are evaluated on circuits of varying complexity and different technologies, showing both the feasibility and portability of the work presented here.
There is still a great reliance on human expert knowledge during the analog integrated circuit sizing design phase due to its complexity and scale, with the result that there is a very low level of automation associated with it. Current research shows that reinforcement learning is a promising approach for addressing this issue. Similarly, it has been shown that the convergence of conventional optimization approaches can be improved by transforming the design space from the geometrical domain into the electrical domain. Here, this design space transformation is employed as an alternative action space for deep reinforcement learning agents. The presented approach is based entirely on reinforcement learning, whereby agents are trained in the craft of analog circuit sizing without explicit expert guidance. After training and evaluating agents on circuits of varying complexity, their behavior when confronted with a different technology, is examined, showing the applicability, feasibility as well as transferability of this approach.
This paper presents a toolbox in Matlab/Octave for procedural design of analog integrated circuits. The toolbox contains all native functions required by analog designers (namely, schematic-generation, simulation setup and execution, integrated look-up tables and functions for design space exploration) to capture an entire design strategy in an executable script. This script - which we call an Expert Design Plan (EDP) - is capable of executing an analog circuit design fully automatically. The toolbox is integrated in an existing design flow. A bandgap reference voltage circuit is designed with this tool in less than 15 min.
Eine neue Methode zur Berechnung von Temperaturen in Bonddrähten umgeben von einem endlichen Mold wird vorgestellt. Sie ist schneller als die übliche Finite Elemente-Methode (FEM), während sie vergleichbare Resultate produziert. Für manche Parameter funktioniert unsere Methode, während die FEM-Methode versagt. Der Algorithmus ist im sogenannten Bondrechner implementiert, der eine leicht zu benutzende Oberfläche für Designer von mikroelektronischen Systemen bereitstellt. Seine Anwendung hat das Potential, die Zuverlässigkeit von Bonddrähten zu verbessern. Ein nichtidealer Parameter für den Wärmetransfer vom Bonddraht zum Mold-Package wurde ebenfalls berücksichtigt. Dieser Parameter ändert sich wahrscheinlich unter Alterseinflüssen und ist daher sehr wichtig für Zuverlässigkeits-Schätzungen. In unserer Methode wird die Wechselwirkung von Nachbardrähten ebenfalls berücksichtigt. Diese wird immer wichtiger, weil der Durchmesser und der wechselseitige Abstand der Bonddrähte sich verringert, wegen der fortschreitenden Miniaturisierung der Chip-Verpackungen. Unser Programm kann ebenfalls Temperaturen für transiente Ströme berechnen und den Strom berechnen, der zu einer gegebenen Maximaltemperatur gehört.
When a bonding wire becomes too hot, it fuses and fails. The ohmic heat that is generated in the wire can be partially dissipated to a mold package. For this cooling effect the thermal contact between wire and package is an important parameter. Because this parameter can degrade over lifetime, the fusing of a bonding wire can also occur as a long-term effect. Another important factor is the thermal power generated in the vicinity of the bond pads. Nowadays, the reliability of bond wires relies on robust dimensioning based on estimations. Smaller package sizes increase the need for better predictive methods.
The Bond Calculator, a new thermo-electrical simulation tool, is able to predict the temperature profiles along bond wires of arbitrary dimensions in dependence on the applied arbitrary transient current profile, the mold surrounding the wire, and the thermal contact between wire and mold.
In this paper we closely investigated the spatial temperature profiles along different bond wires in air in order to make a first step towards the experimental verification of the simulation model. We are using infrared microscopy in order to measure the thermal radiation generated along the bond wire. This is easier to perform quantitatively in air than in the mold package, because of the non-negligible absorbance of the mold material in the infrared wavelength region.
A generic, knowledge-based method for automatic topology selection of analog circuits in a predefined analog reuse library is presented in this paper on the OTA (Operational Transconductance Amplifier) example. Analog circuits of a given circuit class are classified in a topology tree, where each node represents a specific topology. Child nodes evolve from their parent nodes by an enhancement of the parent node’s topological structure. Topology selection is performed by a depth first-search in the topology tree starting at the root node, thus checking topologies of increasing complexity. The decisions at each node are based on solving equations or – if this is not possible – on simulations. The search ends at the first (and thus the simplest) topology which can meet the specification after an adequate circuit sizing. The advantages of the generic, tree based topology selection method presented in this paper are shown in comparison to a pool selection method and to heuristic approaches. The selection is based on an accomplished chip investigation.