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A device including a first and second monitoring unit, the first monitoring unit detecting a first voltage potential and the second monitoring unit detecting a second voltage potential, the monitoring units comparing the first voltage potential and the second voltage potential to the value of the supply voltage and activate a control unit as a function of the comparisons, the control unit determining a switching point in time of a second power transistor, and an arrangement being present which generates current when the second power transistor is being switched on, the current changing the first voltage potential, and the control unit activates a first power transistor when the first voltage potential has the same value as the supply voltage, so that the first power transistor is de-energized.
The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the presented integrated micropower supply. Connected to the 120/230-VRMS mains, it provides a 3.3-V ac output voltage, suitable for applications such as the Internet-of Things and smart homes. The micropower supply consists of a fully integrated ac–dc and dc–dc converter with one external low-voltage surface mount device buffer capacitor, resulting in an extremely compact size. Fabricated in a low-cost 0.35-μm 700-V complimentary metal-oxide-semiconductor technology, it covers a die size of 7.7 mm². The ac–dc converter is a direct coupled, full-wave rectifier with a subsequent series regulator. The dc–dc stage is a fully integrated capacitive 4:1 converter with up to 17-V input and 47.4% peak efficiency. The power supply comprises several high-voltage control circuits including level shifters and various types of charge pumps (CPs). A source supplied CP is utilized that supports a varying switching node potential. The overall losses are discussed and optimized, including flying capacitor bottom-plate losses. The power supply achieves an output power of 3 mW, resulting in a power density of 390 μW/mm². This exceeds prior art by a factor of 11.
Erfindungsgemäß wird ein Verfahren zur Optimierung des Betriebs eines in einem Regelkreis für einen Aufwärtswandler vorgesehenen digitalen Reglers (30) zur Verfügung gestellt. Das Verfahren umfasst die folgenden Verfahrensschritte: Auswerten (S1) mindestens einer Ausgangsgröße des digitalen Reglers im Betrieb des Aufwärtswandlers. Schätzen (S2) des instantanen Lastwiderstandswertes (RL) in der Strecke des Regelkreises anhand der mindestens einen ausgewerteten Ausgangsgröße. Einstellen (S3) mindestens eines Reglerkoeffizienten des digitalen Reglers anhand des geschätzten instantanen Lastwiderstandswertes (RL) im Betrieb des Aufwärtswandlers. Erfindungsgemäß bedingt eine Veränderung in der Einstellung des mindestens einen Reglerkoeffizienten eine Veränderung der Transitfrequenz im Regelkreis. Ferner wird ein Regelkreis für einen Aufwärtswandler mit einem digitalen Regler zur Verfügung gestellt, welcher eingerichtet ist, um die Schritte des erfindungsgemäßen Verfahrens durchzuführen. Des Weiteren wird ein Computerprogrammprodukt mit computerausführbarem Programmcode zur Durchführung des erfindungsgemäßen Verfahrens zur Verfügung gestellt.
This paper presents a dc–dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc–dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130 nm CMOS technology with an area of only 0.14 mm². It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.
This paper presents a wide-Vin step-down parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300-nH resonant coil, placed in parallel to a conventional buck converter. Soft-switching resonant converters are beneficial for high-Vin multi-MHz converters to reduce dominant switching losses, enabling higher switching frequencies. The output filter inductor is optimized based on an empirical study of available inductors. The study shows that faster switching significantly reduces not only the inductor value but also volume, price, and even the inductor losses. In addition, unlike conventional resonant concepts, soft-switching control as part of the proposed PRC eliminates input voltage-dependent losses over a wide operating range, resulting in 76.3% peak efficiency. At Vin = 48 V, a loss reduction of 35% is achieved compared with the conventional buck converter. Adjusting an integrated capacitor array, and selecting the number of oscillation periods, keeps the switching frequency within a narrow range. This ensures high efficiency across a wide range of Vin = 12–48 V, 100–500-mA load, and 5-V output at up to 25-MHz switching frequency. Thanks to the low output current ripple, the output capacitor can be as small
as 50 nF.
This paper presents a fully integrated gate driver in a 180-nm bipolar CMOS DMOS (BCD) technology with 1.5-A max. gate current, suitable for normally OFF gallium nitride (GaN) power switches, including gate-injection transistors (GIT). Full-bridge driver architecture provides a bipolar and three-level gate drive voltage for a robust and efficient GaN switching. The concept of high voltage energy storing (HVES), which comprises an on-chip resonant LC tank, enables a very area-efficient buffer capacitor integration and superior gatedriving speed. It reduces the component count and the influence of parasitic gate-loop inductance. Theory and calculations confirm the benefits of HVES compared to other capacitor implementation methods. The proposed gate driver delivers a gate charge of up to 11.6 nC, sufficient to drive most types of currently available GaN power transistors. Consequently, HVES enables to utilize the fast switching capabilities of GaN for advanced and compact power electronics.
Boost converters suffer from a bandwidth limitation caused by the right-half plane zero (RHPZ), which occurs in the control-to-output transfer function. In contrast, there are many applications that require superior dynamic behavior. Further, size and cost of boost converter systems can be minimized by reduced voltage deviations and fast transient responses in case of large signal load transients. The key idea of the proposed ΔV/Δt-intervention control concept is to adapt the controller output to its new steady state value immediately after a load transient by prediction from known parameters. The concept is implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology and a Xilinx Spartan-6 field programmable gate array (FPGA). In a boost converter with 3.5V input voltage, 6.3V output voltage, 1.2A load, and 500 kHz switching frequency, the output voltage deviations are 2.8x smaller, scaling down the output capacitor value by the same factor. The recovery times are 2.4x shorter in case of large signal load transients with the proposed concept. The control is widely applicable, as it supports constant switching frequencies and allows for duty cycle and inductor current limitations. It also shows various advantages compared to conventional control and to selected adaptive control concepts.
Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ~1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.
A wide-bandwidth galvanically isolated current sensing circuit with an integrated Rogowski coil in 180nm CMOS is presented. Exploiting the high-frequency properties of an optimized on-chip Rogowski coil, currents can be measured up to a bandwidth of 75 MHz. The analog sensor front-end comprises a two-stage integrator, which allows a chopper frequency below signal bandwidth, resulting in 2.2 mVrms output noise. An additional integrated Hall sensor extends the measurement range towards DC.