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Despite 30 years of Electronic Design Automation, analog IC layouts are still handcrafted in a laborious fashion today due to the complex challenge of considering all relevant design constraints. This paper presents Self-organized Wiring and Arrangement of Responsive Modules (SWARM), a novel approach addressing the problem with a multi-agent system: autonomous layout modules interact with each other to evoke the emergence of overall compact arrangements that fit within a given layout zone. SWARM´s unique advantage over conventional optimization-based and procedural approaches is its ability to consider crucial design constraints both explicitly and implicitly. Several given examples show that by inducing a synergistic flow of self-organization, remarkable layout results can emerge from SWARM’s decentralized decision-making model.
In analog layout design, chip floorplans are usually still handcrafted by human experts. Particularly, the nondiscrete variability of block dimensions must be exploited thereby, which is a serious challenge for optimization-based algorithmic floorplanners. This paper presents a fundamentally new automation approach based on self-organization, in which floorplan blocks can autonomously move, rotate and deform themselves to jointly let compact results emerge from a synergistic flow of interaction. Our approach is able to minimize area and wirelength, supports nonslicing floorplan structures, can consider fully variable block dimensions, accounts for a fixed rectilinear boundary, and works absolutely deterministic. The approach is innovatively different from conventional, top-down oriented floorplanning algorithms.
This paper enhances SWARM, a novel deterministic analog layout automation approach based on the idea of cellular automata. SWARM implements a decentralized interaction model in which responsive layout modules, covering basic circuit types, autonomously move, rotate and deform themselves to let constraint-compliant, compact layout solutions emerge from a synergetic flow of self-organization. With the ability to consider design constraints both implicitly and explicitly, SWARM joins the layout quality of procedural generators with the flexibility of optimization algorithms, combining these two kinds of automation into a “bottom-up meets top-down” flow. The new enhancements are demonstrated in an OTA example, depicting the power of SWARM and its enormous potential for future developments.
The limited interfaces of today's IC design environments for editing PCell parameters hinder a solid advancement towards more complex analog PCell modules. This paper presents Hierarchical Instance Parameter Editing (HIPE), a highly flexible concept for the customization of PCell sub-instances. Introducing a new type of parameter, HIPE facilitates the dynamic creation of multi-level editing forms reflecting the actual contents of a PCell instance. This approach greatly improves a PCell's ease-of-use, substantially simplifies PCell development, and allows for a hierarchical execution of parameter validation callbacks. Our HIPE implementation has been integrated into a professional PCell development tool and represents a key enabling technology for upcoming generations of high-level hierarchical PCells.
Optimization-based analog layout automation does not yet find evident acceptance in the industry due to the complexity of the design problem. This paper presents a Self-organized Wiring and Arrangement of Responsive Modules (SWARM), able to consider crucial design constraints both implicitly and explicitly. The flexibility of algorithmic methods and the expert knowledge captured in PCells combine into a flow of supervised module interaction. This novel approach targets the creation of constraint-compliant layout blocks which fit into a specified zone. Provoking a synergetic self-organization, even optimal layout solutions can emerge from the interaction. Various examples depict the power of that new concept and the potential for future developments.
Optimization-based design automation for analog ICs still remains behind the demands. A promising alternative is given by procedural approaches such as parameterized generators, also known as PCells. We are working on a complete analog design flow based on parameterized generators for entire circuits and corresponding layout modules. Because the conventional programming of such enhanced generators is far too complicated and costly, new methods are needed to ease their development. This paper presents gPCDS (graphical PCDS), a novel tool for a designer-oriented development of schematic module generators, integrated into a common schematic entry environment. The tool is based on PCDS (Parameterized Circuit Description Scheme), a meta-language for the creation of parametrized analog circuits. Schematic module generators are a very desirable complement to layout module generators in order to achieve a seamless schematic- driven layout design flow on module level. By facilitating a way of generator development that matches a design expert’s mentality, gPCDS contributes to close this gap in the analog design flow.