Refine
Document Type
- Conference proceeding (12)
- Book chapter (2)
- Journal article (1)
Language
- English (15)
Is part of the Bibliography
- yes (15)
Institute
- Technik (15)
Publisher
- IEEE (11)
- Springer (2)
- Tarquin (1)
- VDE Verlag GmbH (1)
This paper introduces a highly scalable heteromodular origami art technique for constructing 3D framework structures using elementary struts and connectors folded from uncut sheets of standard A4 office paper. The presented technique, named ZEBRA, allows the design of meter-scale architectural objects, such as truss bridges and towers, which are capable of bearing substantial mechanical loads. Moving parts, ranging from simple levers to complete multi-bar linkages, can be integrated into static frameworks using a set of kinematic extensions. An overview is given of how the ZEBRA system can be used to teach university students various theoretical and practical aspects of the engineering sciences in an entertaining and hands-on way.
Verification of an active time constant tuning technique for continuous-time delta-sigma modulators
(2022)
In this work we present a technique to compensate the effects of R-C / g m -C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with finely tunable circuit structures, such as current-steering digital-to-analog converters (DAC). We apply our technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure, implemented in a 0.35-μm CMOS process. A tuning scheme for the reference currents of the feedback DACs is derived as a function of the individual TC errors and verified by circuit simulations. We confirm the tuning technique experimentally on the fabricated circuit over a TC parameter variation range of ±20%. Stable modulator operation is achieved for all parameter sets. The measured performances satisfy the expectations from our theoretical calculations and circuit-level simulations.
Virtual prototyping of integrated mixed-signal smart-sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in combination with a cycle-count accurate temporal decoupling approach to simulate digital components and firmware code execution at high speed while preserving clock cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming communication events. These methods fail in case of non-deterministic, asynchronous events resulting in a possibly invalid simulation result. In this paper, we propose an extension of this method to the case of asynchronous events generated by blackbox sources from which a-priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency and/or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. For an example smart-sensor system model, we show that quasi- periodic events that trigger activities in temporally decoupled processes are handled accurately after the predictor has settled.
Virtual prototyping of integrated mixed-signal smart sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in conjunction with a cycle-count accurate temporal decoupling approach (TD) to simulate digital components and firmware code execution at high speed while preserving clock-cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming inter-process communication events. These methods fail in the case of non-deterministic, asynchronous events, resulting in potentially invalid simulation results. In this paper, we propose an extension to the case of asynchronous events generated by blackbox sources from which a priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. We analyze the theoretical performance of the presented predictive temporal decoupling approach (PTD) by deriving a cost model that expresses the expected simulation effort in terms of key parameters such as time quantum size and CPU time per simulation cycle. For an exemplary smart-sensor system model, we show that quasi-periodic events that trigger activities in TD processes are handled accurately after the predictor has settled.
We present the results of an extensive characterization of the performance and stability of a third-order continuous-time delta-sigma modulator with active coefficient error compensation. Using our previously published coefficient tuning technique, process variation induced R-C time-constant (TC) errors in the forward signal path can be compensated indirectly using continuously tunable DACs in the feedback path. To validate our technique experimentally with a range of real TC variations, we designed a modulator with discretely configurable integration capacitor arrays in a 0.35-μm CMOS process. We configured the capacitors of the fabricated device for a range of total TC variations from -28.4 % to +19.3 % and measured the signal-to-noise ratio (SNR) as a function of the input amplitude before and after compensating the variations electrically using the feedback DACs. The results show that our tuning technique is capable of restoring the desired nominal modulator performance over the entire parameter variation range, including the system’s nominal maximum stable amplitude (MSA).
Reduction of power consumption of digital systems is a major concern especially in modern smart sensor systems. These systems are often only activated on request and their power consumption is therefore dominated by the idle-mode. Power reduction mechanisms such as clock or power gating reduce the activity or leakage in the purely digital circuits. We propose a novel adaptive clocking scheme that optimizes the energy demand using a fine-grained oscillator control on cycle-level. To evaluate our new approach, we analytically analyze the power consumption of the regarded system in comparison with available methods. The power of our new adaptive clocking is shown in an integrated smart sensor for capacitive measurements working in a passive wireless sensor node. Using our methods, we show that the energy demand of the example system is reduced even in the case of continuous measurements that demand for a high activity in the digital circuitry.
Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming tasks of todays complex system on chip (SoC) designs. In contrast to digital system design, AMS designers have to deal with a continuous state space of conservative quantities, highly nonlinear relationships, non-functional influences, etc. enlarging the number of possibly critical scenarios to infinity. In this special session we demonstrate the verification of functional properties using simulative and formal methods. We combine different approaches including automated abstraction and refinement of mixed-level models, state-space discretization as well as affine arithmetic. To reach sufficient verification coverage with reasonable time and effort, we use enhanced simulation schemes to avoid conventional simulation drawbacks.
Nowadays robust, energy-efficient multisensor microsystems often come with heavily restricted power budgets and the characteristic of remaining in certain states for a longer period of time. During this time frame there is no continuous clock signal required which gives the opportunity to suspend the clock until a new transition is requested. In this paper, we present a new topology for on-demand locally clocked finite state machines. The architecture combines a local adaptive clocking approach with synchronous and asynchronous components forming a quasi synchronous system. Using adaptive and local clocking comes with the advantages of reducing the power consumption while saving design effort when no global clock tree is needed. Combining synchronous and asynchronous components is beneficial compared to previous fully asynchronous approaches concerning the design restrictions. The developed topology is verified by the implementation and simulation of a temperature-ADC sensor system realized in a 180 nm process.
Silicon neurons represent different levels of biological details and accuracies as a trade-off between complexity and power consumption. With respect to this trade-off and high similarity to neuron behaviour models, relaxation-type oscillator circuits often yield a good compromise to emulate neurons. In this chapter, two exemplified relaxation-type silicon neurons are presented that emulate neural behaviour with energy consumption under the scale of nJ/spike. The first proposed fully CMOS relaxation SiN is based on mathematical Izhikevich model and can mimic a broad range of physiologically observable spike patterns. The results of kinds of biologically plausible output patterns and coupling process of two SiNs are presented in 0.35 μm CMOS technology. The second type is a novel ultra-low-frequency hybrid CMOS-memristive SiN based on relaxation oscillators and analog memristive devices. The hybrid SiN directly emulates neuron behaviour in the range of physiological spiking frequencies (less than 100 Hz). The relaxation oscillator is implemented and fabricated in 0.13 μm CMOS technology. An autonomous neuronal synchronization process is demonstrated with two relaxation oscillators coupled by an analog memristive device in the measurement to emulate the synchronous behaviour between spiking neurons.
Modern wide bandgap power devices promise higher power conversion performance if the device can be operated reliably. As switching speed increases, the effects of parasitic ringing become more prominent, causing potentially damaging overvoltages during device turn-off. Estimating the expected additional voltage caused by such ringing enables more reliable designs. In this paper, we present an analytical expression to calculate the expected overvoltage caused by parasitic ringing based on parasitic element values and operating point parameters. Simulations and measurements confirm that the expression can be used to find the smallest rise time of the switches’ drain-source voltage for minimum overvoltage. The given expression also allows the prediction of the trade off overvoltage amplitude in case of faster required rise times.