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Universelle OTA-Testbench
(2014)
Es wird eine universell einsetzbare Testbench zur Simulation von integrierten Schaltungen innerhalb der OTA-Schaltungsklasse (Operational Transconductance Amplifier; Transkonduktanzverstärker) vorgestellt. Transkonduktanzverstärker sind in der analogen Schaltungstechnik weit verbreitet und daher von großer Bedeutung. Sie treten sowohl als eigenständige Schaltungen innerhalb eines Chips, sowie als Bestandteil anderer Schaltungen (z.B. als erste und zweite Stufe von Operationsverstärkern) auf. Es kann davon ausgegangen werden, dass heute kaum ein analoger oder Mixed-Signal-Chip gefertigt wird, in dem keine Transkonduktanzverstärker verbaut sind. Die Entscheidungsfindung des Entwicklers bei der Auslegung eines OTAs beruht maßgeblich auf einer anwendungsspezifischen Simulation. Die Erstellung einer eigenen Testbench für jede Anwendung bedeutet allerdings einen hohen Zeitaufwand und erschwert den Vergleich der Simulationsergebnisse unterschiedlicher Schaltungsvarianten. Durch eine universelle Testbench kann zum einen der Zeitaufwand verringert werden, zum anderen können nun Simulationsergebnisse direkt miteinander verglichen werden. Hierdurch wird die Entscheidungsfindung des Entwicklers objektiviert und beschleunigt. Neben dem Vergleich unterschiedlicher Schaltungen innerhalb einer Technologie ist auch der Vergleich einer Schaltung in unterschiedlichen Technologien denkbar. Die Idee einer universell anwendbaren Testbench lässt sich auch auf andere analoge Schaltungsklassen anwenden und damit als Prinzip verallgemeinern.
In der Mikroelektronik werden Chips häufig in Mold-Gehäusen verpackt. Die elektrischen Verbindungen vom Chip zu den Anschlussbeinchen des Gehäuses werden mit Bonddrähten realisiert. Für die Berechnung der Gleichgewichtstemperatur in einem Bonddraht bei konstantem Strom sowie von Temperaturverläufen bei transienten Strömen ist die herkömmliche FEM-Methode langsam und unhandlich. Daher wurde der Bondrechner entwickelt, der ein zylindersymmetrisches Ersatz-Modell für das Package in geeigneten mathematischen Gleichungen abbildet.
Im Gegensatz zum Bondrechner der ersten Generation [1], der auf den Gleichungen von [2] basiert, bietet ein neuer mathematischer Ansatz die Möglichkeit, eine endliche effektive Package-Größe, sowie einen endlichen Wärmeübergang zwischen Bonddraht und Mold-Masse zu berücksichtigen. Ebenso wurde die Berechnung der Interaktion von mehreren benachbarten Drähten verfeinert. Die Berechnung von beliebigen transienten Pulsformen mittlerer Länge wurde ebenfalls verbessert. Eine quadratische Komponente in der Temperaturabhängigkeit des spezifischen Widerstandes des Drahtmaterials kann jetzt ebenfalls berücksichtigt werden.
Die Ergebnisse wurden erfolgreich mit FEM-Berechnungen verglichen und die Geschwindigkeit der Berechnung ist um Größenordnungen schneller als mit kommerziellen FEM-Programmen.
Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM verification to robust (pro-active) EM aware design - where the circuit layout is designed with individual EM-robust solutions - is urgently needed. This tutorial will give an overview of EM and its effects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its specific characteristics that can be affected during physical design. Examples of EM countermeasures which are applied in today’s commercial design flows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission proiles to obtain application-oriented current density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post layout EM verification towards an EM aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit’s reliability.
Electronic design automation approaches can roughly be divided into optimizers and procedures. While the former have enabled highly automated synthesis flows for digital integrated circuits, the latter play a vital (but mostly underestimated role) in the analog domain. This paper describes both automation strategies in comparison, identifying two fundamentally different automation paradigms that reflect the two basic design practices known as “top-down” and “bottom-up”. Then, with a focus on the latter, the history of procedural approaches is traced from their
early beginnings until today’s evolvements and future prospects to underline their practical importance and to accentuate their scientific value, both in itself and in the overall context of EDA.
When a bonding wire becomes too hot, it fuses and fails. The ohmic heat that is generated in the wire can be partially dissipated to a mold package. For this cooling effect the thermal contact between wire and package is an important parameter. Because this parameter can degrade over lifetime, the fusing of a bonding wire can also occur as a long-term effect. Another important factor is the thermal power generated in the vicinity of the bond pads. Nowadays, the reliability of bond wires relies on robust dimensioning based on estimations. Smaller package sizes increase the need for better predictive methods.
The Bond Calculator, a new thermo-electrical simulation tool, is able to predict the temperature profiles along bond wires of arbitrary dimensions in dependence on the applied arbitrary transient current profile, the mold surrounding the wire, and the thermal contact between wire and mold.
In this paper we closely investigated the spatial temperature profiles along different bond wires in air in order to make a first step towards the experimental verification of the simulation model. We are using infrared microscopy in order to measure the thermal radiation generated along the bond wire. This is easier to perform quantitatively in air than in the mold package, because of the non-negligible absorbance of the mold material in the infrared wavelength region.
We discuss the fabrication technologies for IC chips in this chapter. We will focus on the main process steps and especially on those aspects that are of particular importance for understanding how they affect, and in some cases drive, the layout of ICs. All our analyses in this chapter will be for silicon as the base material; the principles and understanding gained can be applied to other substrates as well. Following a brief introduction to the fundamentals of IC fabrication (Sect. 2.1) and the base material used in it, namely silicon (Sect. 2.2), we discuss the photolithography process deployed for all structuring work in Sect. 2.3. We will then present in Sect. 2.4 some theoretical opening remarks on typical phenomena encountered in IC fabrication. Knowledge of these phenomena is very useful for understanding the process steps we cover in Sects. 2.5–2.8. We examine a simple exemplar process in Sect. 2.9 and observe how a field-effect transistor (FET) – the most important device in modern integrated circuits—is created. To drive the key points home, we provide a review of each topic at the end of every section from the point of view of layout design by discussing relevant physical design aspects.
Optimization-based analog layout automation does not yet find evident acceptance in the industry due to the complexity of the design problem. This paper presents a Self-organized Wiring and Arrangement of Responsive Modules (SWARM), able to consider crucial design constraints both implicitly and explicitly. The flexibility of algorithmic methods and the expert knowledge captured in PCells combine into a flow of supervised module interaction. This novel approach targets the creation of constraint-compliant layout blocks which fit into a specified zone. Provoking a synergetic self-organization, even optimal layout solutions can emerge from the interaction. Various examples depict the power of that new concept and the potential for future developments.
Despite 30 years of Electronic Design Automation, analog IC layouts are still handcrafted in a laborious fashion today due to the complex challenge of considering all relevant design constraints. This paper presents Self-organized Wiring and Arrangement of Responsive Modules (SWARM), a novel approach addressing the problem with a multi-agent system: autonomous layout modules interact with each other to evoke the emergence of overall compact arrangements that fit within a given layout zone. SWARM´s unique advantage over conventional optimization-based and procedural approaches is its ability to consider crucial design constraints both explicitly and implicitly. Several given examples show that by inducing a synergistic flow of self-organization, remarkable layout results can emerge from SWARM’s decentralized decision-making model.
Lithographical hotspot (LH) detection using deep learning (DL) has received much attention in the recent years. It happens mainly due to the facts the DL approach leads to a better accuracy over the traditional, state-of-the-art programming approaches. The purpose of ths study is to compare existing data augmentation (DA) techniques for the integrated circuit (IC) mask data using DL methods. DA is a method which refers to the process of creating new samples similar to the training set, thereby helping to reduce the gap between classes as well as improving the performance of the DL system. Experimental results suggest that the DA methods increase overall DL models performance for the hotspot detection tasks.
Analog integrated circuit sizing is notoriously difficult to automate due to its complexity and scale; thus, it continues to heavily rely on human expert knowledge. This work presents a machine learning-based design automation methodology comprising pre-defined building blocks such as current mirrors or differential pairs and pre-computed look-up tables for electrical characteristics of primitive devices. Modeling the behavior of primitive devices around the operating point with neural networks combines the speed of equation-based methods with the accuracy of simulation-based approaches and, thereby, brings quality of life improvements for analog circuit designers using the gm/Id method. Extending this procedural automation method for human design experts, we present a fully autonomous sizing approach. Related work shows that the convergence properties of conventional optimization approaches improve significantly when acting in the electrical domain instead of the geometrical domain. We, therefore, formulate the circuit sizing task as a sequential decision-making problem in the alternative electrical design space. Our automation approach is based entirely on reinforcement learning, whereby abstract agents learn efficient design space navigation through interaction and without expert guidance. These agents’ learning behavior and performance are evaluated on circuits of varying complexity and different technologies, showing both the feasibility and portability of the work presented here.