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Boost converters suffer from a bandwidth limitation caused by the right-half plane zero (RHPZ), which occurs in the control-to-output transfer function. In contrast, there are many applications that require superior dynamic behavior. Further, size and cost of boost converter systems can be minimized by reduced voltage deviations and fast transient responses in case of large signal load transients. The key idea of the proposed ΔV/Δt-intervention control concept is to adapt the controller output to its new steady state value immediately after a load transient by prediction from known parameters. The concept is implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology and a Xilinx Spartan-6 field programmable gate array (FPGA). In a boost converter with 3.5V input voltage, 6.3V output voltage, 1.2A load, and 500 kHz switching frequency, the output voltage deviations are 2.8x smaller, scaling down the output capacitor value by the same factor. The recovery times are 2.4x shorter in case of large signal load transients with the proposed concept. The control is widely applicable, as it supports constant switching frequencies and allows for duty cycle and inductor current limitations. It also shows various advantages compared to conventional control and to selected adaptive control concepts.
This paper presents a digitally controlled boost converter IC for high output voltage and fast transient applications. Thus, it is well applicable in automotive and industrial environments. The 3V-to-6V input voltage, 6.3V output voltage, 1A boost converter IC is fabricated in a 180nm BCD technology. Digital control enables cost savings, advanced control concepts, and it is less parameter sensitive compared to common analog control. A 90 ns latency, 6-bit delay line ADC operates with a window concept, meeting high resolution requirements, e.g. in car battery applications. An output voltage live tracking is included for extending the ADC conversion window. A charge pump DAC provides high resolution, monotonicity, and short 128 ns conversion time. Further, a standard digital PI controller is enhanced by a simple but effective ΔV/Δt-intervention control. It results in 2.8x reduced output voltage deviations in case of load steps, scaling down the output capacitor value by the same factor.
Erfindungsgemäß wird ein Verfahren zur Optimierung des Betriebs eines in einem Regelkreis für einen Aufwärtswandler vorgesehenen digitalen Reglers (30) zur Verfügung gestellt. Das Verfahren umfasst die folgenden Verfahrensschritte: Auswerten (S1) mindestens einer Ausgangsgröße des digitalen Reglers im Betrieb des Aufwärtswandlers. Schätzen (S2) des instantanen Lastwiderstandswertes (RL) in der Strecke des Regelkreises anhand der mindestens einen ausgewerteten Ausgangsgröße. Einstellen (S3) mindestens eines Reglerkoeffizienten des digitalen Reglers anhand des geschätzten instantanen Lastwiderstandswertes (RL) im Betrieb des Aufwärtswandlers. Erfindungsgemäß bedingt eine Veränderung in der Einstellung des mindestens einen Reglerkoeffizienten eine Veränderung der Transitfrequenz im Regelkreis. Ferner wird ein Regelkreis für einen Aufwärtswandler mit einem digitalen Regler zur Verfügung gestellt, welcher eingerichtet ist, um die Schritte des erfindungsgemäßen Verfahrens durchzuführen. Des Weiteren wird ein Computerprogrammprodukt mit computerausführbarem Programmcode zur Durchführung des erfindungsgemäßen Verfahrens zur Verfügung gestellt.
Size and cost of a boost converter can be minimized by reducing the voltage overshoot and fastening the transient response in case of load transient. The presented technique improves the transient response of a current mode controlled boost converter, which usually suffers from bandwidth limitation because of its right-half-plane zero (RHPZ). The proposed technique comprises a load current estimation which works as part of a digital controller without any additional measurements. Based on the latest load estimation the controller parameters are adapted, achieving small voltage overshoot and fast transient response. The presented technique was implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology, a Xilinx Spartan-6 field programmable gate array (FPGA), and a TI-ADS8422 analog to-digital-converter (ADC). Simulation and measurements of a 4V-to-6.3V, 500mA boost converter show an improvement of 50% in voltage overshoot and response time to load transient.
Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time.
Digital control design bears challenges like the prevention of limit cycle oscillations and controller wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digitalconverter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital converters in digitally controlled SMPS.
Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 μs-latency of a 16-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies.
Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.
