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We present a new methodology for automatic selection and sizing of analog circuits demonstrated on the OTA circuit class. The methodology consists of two steps: a generic topology selection method supported by a “part-sizing” process and subsequent final sizing. The circuit topologies provided by a reuse library are classified in a topology tree. The appropriate topology is selected by traversing the topology tree starting at the root node. The decision at each node is gained from the result of the part-sizing, which is in fact a node-specific set of simulations. The final sizing is a simulation-based optimization. We significantly reduce the overall simulation effort compared to a classical simulation-based optimization by combining the topology selection with the part-sizing process in the selection loop. The result is an interactive user friendly system, which eases the analog designer’s work significantly when compared to typical industrial practice in analog circuit design. The topology selection method and sizing process are implemented as a tool into a typical analog design environment. The design productivity improvement achievable by our method is shown by a comparison to other design automation approaches.
The presented wide-Vin step-down converter introduces a parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300 nH resonant coil, placed in parallel to a conventional buck converter. Unlike conventional resonant concepts, the implemented soft-switching control eliminates input voltage dependent losses over a wide operating range. This ensures high efficiency across a wide range of Vin= 12-48V, 100-500mA load and 5V output at up to 15MHz switching frequency. The peak efficiency of the converter is 76.3 %. Thanks to the low output current ripple, the output capacitor can be as small as 50 nF, while the inductor tolerates a larger ESR, resulting in small component size. The proposed PRC architecture is also suitable for future power electronics applications using fast-switching GaN devices.
Erfindungsgemäß wird ein Verfahren zur Optimierung des Betriebs eines in einem Regelkreis für einen Aufwärtswandler vorgesehenen digitalen Reglers (30) zur Verfügung gestellt. Das Verfahren umfasst die folgenden Verfahrensschritte: Auswerten (S1) mindestens einer Ausgangsgröße des digitalen Reglers im Betrieb des Aufwärtswandlers. Schätzen (S2) des instantanen Lastwiderstandswertes (RL) in der Strecke des Regelkreises anhand der mindestens einen ausgewerteten Ausgangsgröße. Einstellen (S3) mindestens eines Reglerkoeffizienten des digitalen Reglers anhand des geschätzten instantanen Lastwiderstandswertes (RL) im Betrieb des Aufwärtswandlers. Erfindungsgemäß bedingt eine Veränderung in der Einstellung des mindestens einen Reglerkoeffizienten eine Veränderung der Transitfrequenz im Regelkreis. Ferner wird ein Regelkreis für einen Aufwärtswandler mit einem digitalen Regler zur Verfügung gestellt, welcher eingerichtet ist, um die Schritte des erfindungsgemäßen Verfahrens durchzuführen. Des Weiteren wird ein Computerprogrammprodukt mit computerausführbarem Programmcode zur Durchführung des erfindungsgemäßen Verfahrens zur Verfügung gestellt.
This paper presents a wide-Vin step-down parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300-nH resonant coil, placed in parallel to a conventional buck converter. Soft-switching resonant converters are beneficial for high-Vin multi-MHz converters to reduce dominant switching losses, enabling higher switching frequencies. The output filter inductor is optimized based on an empirical study of available inductors. The study shows that faster switching significantly reduces not only the inductor value but also volume, price, and even the inductor losses. In addition, unlike conventional resonant concepts, soft-switching control as part of the proposed PRC eliminates input voltage-dependent losses over a wide operating range, resulting in 76.3% peak efficiency. At Vin = 48 V, a loss reduction of 35% is achieved compared with the conventional buck converter. Adjusting an integrated capacitor array, and selecting the number of oscillation periods, keeps the switching frequency within a narrow range. This ensures high efficiency across a wide range of Vin = 12–48 V, 100–500-mA load, and 5-V output at up to 25-MHz switching frequency. Thanks to the low output current ripple, the output capacitor can be as small
as 50 nF.
Boost converters suffer from a bandwidth limitation caused by the right-half plane zero (RHPZ), which occurs in the control-to-output transfer function. In contrast, there are many applications that require superior dynamic behavior. Further, size and cost of boost converter systems can be minimized by reduced voltage deviations and fast transient responses in case of large signal load transients. The key idea of the proposed ΔV/Δt-intervention control concept is to adapt the controller output to its new steady state value immediately after a load transient by prediction from known parameters. The concept is implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology and a Xilinx Spartan-6 field programmable gate array (FPGA). In a boost converter with 3.5V input voltage, 6.3V output voltage, 1.2A load, and 500 kHz switching frequency, the output voltage deviations are 2.8x smaller, scaling down the output capacitor value by the same factor. The recovery times are 2.4x shorter in case of large signal load transients with the proposed concept. The control is widely applicable, as it supports constant switching frequencies and allows for duty cycle and inductor current limitations. It also shows various advantages compared to conventional control and to selected adaptive control concepts.
This paper presents a digitally controlled boost converter IC for high output voltage and fast transient applications. Thus, it is well applicable in automotive and industrial environments. The 3V-to-6V input voltage, 6.3V output voltage, 1A boost converter IC is fabricated in a 180nm BCD technology. Digital control enables cost savings, advanced control concepts, and it is less parameter sensitive compared to common analog control. A 90 ns latency, 6-bit delay line ADC operates with a window concept, meeting high resolution requirements, e.g. in car battery applications. An output voltage live tracking is included for extending the ADC conversion window. A charge pump DAC provides high resolution, monotonicity, and short 128 ns conversion time. Further, a standard digital PI controller is enhanced by a simple but effective ΔV/Δt-intervention control. It results in 2.8x reduced output voltage deviations in case of load steps, scaling down the output capacitor value by the same factor.
Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time.
Digital control design bears challenges like the prevention of limit cycle oscillations and controller wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digitalconverter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital converters in digitally controlled SMPS.
Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 μs-latency of a 16-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies.
Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.
Die Spannungsversorgung elektronischer Steuergeräte im Automotive-Bereich wird zunehmend durch Schaltregler sichergestellt. Der SEPIC (Single Ended Primary Inductance Converter) besitzt die Eigenschaft, eine Spannung aufwärts wie auch abwärts wandeln zu können und könnte somit klassische Buck- und Boost-Wandler ablösen. Dieser Beitrag untersucht den SEPIC hinsichtlich Eignung für Automotive-Anwendungen. Dazu wurde eine Groß- sowie Kleinsignalanalyse am Wandler durchgeführt, mit geeigneten Simulationsmodellen nachgebildet und Messungen gegenüber gestellt. Der SEPIC zeigt als Hauptvorteile:
1. einen verzugsfreien Übergang zwischen Buck-/Boost Betrieb, 2. geringe Eingangswelligkeit, 3.DC-Kurzschlussfestigkeit. Auch hinsichtlich Wirkungsgrad und EMV-Verhalten stellt der SEPIC eine interessante Alternative dar. Der zwischen Ein- und Ausgang liegende Kondensator wird dauerhaft von einem Strom durchflossen, auf Basis der Effektivströme wird das damit verbundene Ausfallrisiko diskutiert.
An integrated synchronous buck converter with a high resolution dead time control for input voltages up to 48V and 10MHz switching frequency is presented. The benefit of an enhanced dead time control at light loads to enable zero voltage switching at both the high-side and low-side switch at low output load is studied. This way, compact multi-MHz DCDC converters can be implemented at high efficiency over a wide load current range. The concept also eliminates body diode forward conduction losses and minimizes reverse recovery losses. A dead time resolution of 125 ps is realized by an 8-bit differential delay chain. A further efficiency enhancement by soft switching at the high-side switch at light load is achieved with a voltage boost of the switching node by dead time control in forced continuous conduction mode. The monolithic converter is implemented in an 180nm high-voltage BiCMOS technology. At V IN = 48V, V OUT = 5V, 50mA load, 10MHz switching frequency and 500 nH output inductance, the efficiency is measured to be increased by 14.4% compared to a conventional predictive dead time control. A peak efficiency of 80.9% is achieved at 12V input.
