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In this paper, we address the novel EDP (Expert Design Plan) principle for procedural design automation of analog integrated circuits, which captures the knowledge-based design strategy of human circuit designers in an executable script, making it reusable. We present the EDP Player, which enables the creation and execution of EDPs for arbitrary circuits in the Cadence® Virtuoso® Design Environment. The tool provides a generic version of an instruction set, called EDPL (EDPLanguage), enabling emulation of a typical manual analog sizing flow. To automate the design of a Miller Operational Amplifier and to create variants of a Smart Power IC, several EDPs were implemented using this tool. Employing these EDPs leads to a strong reduction of design time without compromising design quality or reliability.
This paper presents a machine learning powered, procedural sizing methodology based on pre-computed look-up tables containing operating point characteristics of primitive devices. Several Neural Networks are trained for 90nm and 45nm technologies, mapping different electrical parameters to the corresponding dimensions of a primitive device. This transforms the geometric sizing problem into the domain of circuit design experts, where the desired electrical characteristics are now inputs to the model. Analog building blocks or entire circuits are expressed as a sequence of model evaluations, capturing the sizing strategy and intention of the designer in a procedure, which is reusable across different technology nodes. The methodology is employed for the sizing of two operational amplifiers, and evaluated for two technology nodes, showing the versatility and efficiency of this approach.
There is still a great reliance on human expert knowledge during the analog integrated circuit sizing design phase due to its complexity and scale, with the result that there is a very low level of automation associated with it. Current research shows that reinforcement learning is a promising approach for addressing this issue. Similarly, it has been shown that the convergence of conventional optimization approaches can be improved by transforming the design space from the geometrical domain into the electrical domain. Here, this design space transformation is employed as an alternative action space for deep reinforcement learning agents. The presented approach is based entirely on reinforcement learning, whereby agents are trained in the craft of analog circuit sizing without explicit expert guidance. After training and evaluating agents on circuits of varying complexity, their behavior when confronted with a different technology, is examined, showing the applicability, feasibility as well as transferability of this approach.
Condition monitoring (CM) is crucial for ensuring equipment reliability. Yet, its practical implementation encounters several challenges. On the one hand, these include hurdles in big data collection/ storage, sensor selection/calibration/ installation. On the other hand, developing effective CM techniques, especially for anomaly detection throughout the degradation process, requires extracting and selecting appropriate Health Indicators (HI) and ensuring accurate anomaly detection. While bearings and gears have been intensively studied in the past, only little attention has been given to roller chain systems. Therefore, this study introduces an innovative approach leveraging a sensorless strategy and Deep Weighted K-Nearest Neighborhood (DWKNN) for detecting the abnormal status in roller chain systems. Firstly, by utilizing readily available motor driver data, the need for expensive sensor selection/installation and data management is eliminated, enhancing cost-effectiveness and applicability across diverse industrial applications. Secondly, leveraging position information from the motor, the raw data is segmented, transformed into the frequency domain, and fused to provide a comprehensive understanding of the system’s behavior, thus improving CM performance. Subsequently, DWKNN entails blind indicator extraction and anomaly detection. Blind indicator extraction utilizes the Deep Sparse Autoencoder (DSAE) method to dig hidden information in the acquired data and represent the degradation process. Meanwhile, anomaly detection is achieved through a weighted KNN, ensuring effectiveness and robustness. Through validation on multiple chains, the developed methodology demonstrates its effectiveness in addressing real-world CM challenges in industrial environments, offering a cost-effective and reliable solution compared to other methods.
Analog and mixed-signal (A/MS) IC design is still a largely manual process. It lags far behind its digital counterpart were synthesis methods automate many key design steps. This advantage in digital roots from the possibility of a high degree of abstraction with manageable information loss from which a highly systematic digital flow arose. Not only does it incorporate automation throughout, but it also links the individual flow steps by well-defined interfaces. In analog, to the contrary, both a comparable flow approach and automation is largely missing. Even though key design steps, such as schematic and layout, are meanwhile linked well, other important steps, like breaking down a specification to a suitable topology, are not yet in place. Therefore, design teams develop individual design approaches in order to handle the complexity of analog design all the way from specification to layout. A major challenge is the lack of reproducibility, which roots from the lack of expert knowledge stored in the design data. Thus, in this tutorial paper, we address the shortcomings of the A/MS design flow and discuss how knowledge-based automaton methods can both systematize and automate key design steps. Also, we discuss how the steps can be linked together in order to form a systematic design flow. Our proposed A/MS IC design design flow considers automation from specification over schematic level to the layout level.
Analog integrated circuit sizing still relies heavily on human expert knowledge as previous automation approaches have not found wide-spread acceptance in industry. One strand, the optimization-based automation, is often discarded due to inflated constraining setups, infeasible results or excessive run times. To address these deficits, this work proposes a alternative optimization flow featuring a designer’s intuition for feasible design spaces through integration of expert knowledge based on the gm/ID-method. Moreover, the extensive run times of simulation-based optimization flows are overcome by incorporating computationally efficient machine learning methods. Neural network surrogate models predicting eleven performance parameters increase the evaluation speed by 3 400× on average compared to a simulator. Additionally, they enable the use of optimization algorithms dependent on automatic differentiation, that would otherwise be unavailable in this field. First, an up to 4× more efficient way for sampling training data based on the aforementioned space is detailed. After presenting the architecture and training effort regarding the surrogate models, they are employed as part of the objective function for sizing three operational amplifiers with three different optimization algorithms. Additionally, the benefits of using the gm/ID-method become evident when considering technology migration, as previously found solutions may be reused for other technologies.
Research in design automation for power electronics (DAPE) is a growing subject propelled by the demand for power electronics in the light of electrification. This paper explains and transfers concepts found in microelectronics EDA to DAPE. A broad literature analysis via automated rule-based classification of more than 6 000 publications shows the dominant automation approaches in connection with popular tasks to automate, the focused components and respective applications. Besides this content analysis, an analysis over time provides insight into past and current trends. The paper concludes with a comparison to EDA found in analog IC design to outline possible future research directions in DAPE.
Analog integrated circuit sizing is notoriously difficult to automate due to its complexity and scale; thus, it continues to heavily rely on human expert knowledge. This work presents a machine learning-based design automation methodology comprising pre-defined building blocks such as current mirrors or differential pairs and pre-computed look-up tables for electrical characteristics of primitive devices. Modeling the behavior of primitive devices around the operating point with neural networks combines the speed of equation-based methods with the accuracy of simulation-based approaches and, thereby, brings quality of life improvements for analog circuit designers using the gm/Id method. Extending this procedural automation method for human design experts, we present a fully autonomous sizing approach. Related work shows that the convergence properties of conventional optimization approaches improve significantly when acting in the electrical domain instead of the geometrical domain. We, therefore, formulate the circuit sizing task as a sequential decision-making problem in the alternative electrical design space. Our automation approach is based entirely on reinforcement learning, whereby abstract agents learn efficient design space navigation through interaction and without expert guidance. These agents’ learning behavior and performance are evaluated on circuits of varying complexity and different technologies, showing both the feasibility and portability of the work presented here.
