621 Angewandte Physik
Refine
Document Type
- Conference proceeding (40)
- Book chapter (6)
- Patent / Standard / Guidelines (3)
- Journal article (2)
- Anthology (1)
Is part of the Bibliography
- yes (52)
Institute
- Technik (43)
- ESB Business School (5)
- Informatik (4)
Publisher
- IEEE (16)
- Hochschule Ulm (6)
- Springer (5)
- Hanser (2)
- Technische Universität Darmstadt (2)
- VDE-Verlag (2)
- British Institute of Non-Destructive Testing (1)
- Elsevier (1)
- GRID-FTN (1)
- Hochschule Furtwangen (1)
Condition Monitoring for mechanical systems like bearings or transmissions is often done by analysing frequency spectra obtained from accelerometers mounted to the components under observation. Although this approach gives a high amount on information about the system behaviour, the interpretation of the resulting spectra requires expert knowledge, that is, a deep understanding of the effect on condition deterioration on the measured spectra. However, an increasing number of condition monitoring applications demands other representations of the measured signals that can be easily interpreted even by non–experts. Therefore, the objective of this paper is to develop an approach for processing measured process data in order to obtain an easy to interpret measure for assessing the component condition. The main idea is to evaluate the deterioration of a component condition by computing the correlation function of current measurements with past measurements in order to detect a component condition deterioration from a change in these correlation functions. Besides the simplicity of the obtained measure, this approach opens the opportunity for integrating a model based approach as well. The developed method is tested based on a condition monitoring application in a roller chain.
This work presents a spiral antenna array, which can be used in the V- and W-Band. An array equipped with Dolph-Chebychev coefficients is investigated to address issues related to the low gain and side lobe level of the radiating structure. The challenges encountered in this achievement are to provide an antenna that is not only good matched but also presents an appreciable effective bandwidth at the frequency bands of interest. Its radiation properties including the effective bandwidth and the gain are analyzed for the W-Band.
The superior electrical and thermal properties of silicon carbide (SiC) allow further shrinking of the active area of future power semiconductor devices. A lower boundary of the die size can be obtained from the thermal impedance required to withstand the high power dissipation during a short-circuit event. However, this implies that the power distribution is homogeneous and that no current filamentation has to be considered. Therefore, this work investigates this assumption by evaluating the stability of a SiC-MOSFET over a wide range of operation conditions by measurements up to destruction, thermal simulations, and high-temperature characterization.
This paper addresses the turn-on switching process of insulated-gate bipolar transistor (IGBT) modules with anti-parallel free-wheeling diodes (FWD) used in inductive load switching power applications. An increase in efficiency, i.e. decrease in switching losses, calls for a fast switching process of the IGBT, but this commonly implies high values of the reverse-recovery current overshoot. To overcome this undesired behaviour, a solution was proposed which achieves an independent control of the collector current slope and peak reverse recovery current by applying a gate current that is briefly turned negative during the turn-on process. The feasibility of this approach has already been shown, however, a sophisticated control method is required for applying it in applications with varying currents, temperature and device parameters. In this paper a solution based on an adaptive, iterative closed-loop ontrol is proposed. Its effectiveness is demonstrated by experimental results from a 1200 V/200A IGBT power module for different load currents and reverse-recovery current overshoots.
Induced by a societal decision to phase out conventional energy production - the so-called Energiewende (energy transition) - the rise of distributed generation acts as a game changer within the German energy market. The share of electricity produced from renewable resources increased to 31,6% in 2015 (UBA, 2016) with a targeted share of renewable resources in the electricity mix of 55%-60% in 2035 (RAP, 2015), opening perspectives for new products and services. Moreover, the rapidly increasing degree of digitization enables innovative and disruptive business models in niches at the grid's edge that might be the winners of the future. It also stimulates the market entry of newcomers and competitors from other sectors, such as IT or telecommunication, challenging the incumbent utilities. For example, virtual and decentral market places for energy are emerging; a trend that is likely to speed up considerably by blockchain technology, if the regulatory environment is adjusted accordingly. Consequently, the energy business is turned upside down, with customers now being at the wheel. For instance, more than one-third of the renewable production capacities are owned by private persons (Trendsearch, 2013). Therefore, the objective of this chapter is to examine private energy consumer and prosumer segments and their needs to derive business models for the various decentralized energy technologies and services. Subsequently, success factors for dealing with the changing market environment and consequences of the potentially disruptive developments for the market structure are evaluated.
This book showcases new and innovative approaches to biometric data capture and analysis, focusing especially on those that are characterized by non-intrusiveness, reliable prediction algorithms, and high user acceptance. It comprises the peer-reviewed papers from the international workshop on the subject that was held in Ancona, Italy, in October 2014 and featured sessions on ICT for health care, biometric data in automotive and home applications, embedded systems for biometric data analysis, biometric data analysis: EMG and ECG, and ICT for gait analysis. The background to the book is the challenge posed by the prevention and treatment of common, widespread chronic diseases in modern, aging societies. Capture of biometric data is a cornerstone for any analysis and treatment strategy. The latest advances in sensor technology allow accurate data measurement in a non-intrusive way, and in many cases it is necessary to provide online monitoring and real-time data capturing to support a patient’s prevention plans or to allow medical professionals to access the patient’s current status. This book will be of value to all with an interest in this expanding field.
Besides the optimisation of the car, energy-efficiency and safety can also be increased by optimising the driving behaviour. Based on this fact, a driving system is in development whose goal is to educate the driver in energy efficient and safe driving. It monitors the driver, the car and the environment and gives energy-efficiency and safety relevant recommendations. However, the driving system tries not to distract or bother the driver by giving recommendations for example during stressful driving situations or when the driver is not interested in that recommendation. Therefore, the driving system monitors the stress level of the driver as well as the reaction of the driver to a given recommendation and decideswhether to give a recommendation or not. This allows to suppress recommendations when needed and, thus, to increase the road safety and the user acceptance of
the driving system.
A lot of people need help in their daily life to wash, select and manage their clothing. The goal of this work is to design an assistant system (eKlarA) to support the user by giving recommendations to choose the clothing combinations, to find the clothing and to wash the clothing. The idea behind eKlarA is to generate a system that uses sensors to identify the clothing and their state in the clothing cycle. The clothing cycle consists of the stations: closets, laundry basket and washing machine in one or several places. The system uses the information about the clothing, weather and calendar to support the user in the different steps of the clothing cycle. The first prototype of this system has been developed and tested. The test results are presented in this work.
Stress is becoming an important topic in modern life. The influence of stress results in a higher rate of health disorders such as burnout, heart problems, obesity, asthma, diabetes, depressions and many others. Furthermore individual’s behavior and capabilities could be directly affected leading to altered cognition, inappropriate decision making and problem solving skills. In a dynamic and unpredictable environment, such as automotive, this can result in a higher risk for accidents. Different papers faced the estimation as well as prediction of drivers’ stress level during driving. Another important question is not only the stress level of the driver himself, but also the influence on and of a group of other drivers in the near area. This paper proposes a system, which determines a group of drivers in a near area as clusters and it derives the individual stress level. This information will be analyzed to generate a stress map, which represents a graphical view about road section with a higher stress influence. Aggregated data can be used to generate navigation routes with a lower stress influence to decrease stress influenced driving as well as improve road safety.
Die vorliegende Erfindung betrifft ein Transmission Line Pulssystem zum Erzeugen eines elektrischen Pulses, sowie ein diesbezügliches Verfahren. Dabei umfasst das Transmission Line Pulssystem: eine Transmission Line, eine Energieversorgungsquelle zum Aufladen der Transmission Line und einen Entladungsschalter zum Auslösen einer Entladung der aufgeladenen Transmission Line, dadurch gekennzeichnet, dass die Transmission Line eine Vielzahl von Einzelsegmenten umfasst, wobei jedes Einzelsegment über ein zugehöriges Einstellglied mit einem gemeinsamen Massepotential elektrisch verbunden ist, und wobei zumindest eines der Einstellglieder einen Einstellkondensator und einen Einstellschalter aufweist.
Die vorliegende Erfindung betrifft eine Schaltungsanordnung mit einer Bootstrap-Schaltung, die zumindest eine Hauptkapazität aufweist, von der die erste Seite mit einem ersten Zweig der Schaltungsanordnung und die zweite Seite mit einem auf veränderlichem Potential liegenden zweiten Zweig der Schaltungsanordnung verbunden ist. Die vorgeschlagene Schaltungsanordnung zeichnet sich dadurch aus, dass die Bootstrap-Schaltung parallel zur Hauptkapazität wenigstens eine weitere Kapazität aufweist, die über eine zweite Versorgungsspannung auf eine höhere Spannung aufladbar ist als die Hauptkapazität und über wenigstens ein Schaltelement zur Unterstützung der Hauptkapazität zuschaltbar ist. Bei der vorgeschlagenen Schaltungsanordnung kann in Abhängigkeit von der Dimensionierung der Bootstrap-Kapazitäten eine sehr viel kleinere Fläche mit höherem oder gleich bleibenden Spannungseinbruch oder eine nicht so starke Flächenreduzierung mit kleinerem Spannungseinbruch verglichen mit einer herkömmlichen Bootstrap-Schaltung erzielt werden.
Virtual prototyping of integrated mixed-signal smart sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in conjunction with a cycle-count accurate temporal decoupling approach (TD) to simulate digital components and firmware code execution at high speed while preserving clock-cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming inter-process communication events. These methods fail in the case of non-deterministic, asynchronous events, resulting in potentially invalid simulation results. In this paper, we propose an extension to the case of asynchronous events generated by blackbox sources from which a priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. We analyze the theoretical performance of the presented predictive temporal decoupling approach (PTD) by deriving a cost model that expresses the expected simulation effort in terms of key parameters such as time quantum size and CPU time per simulation cycle. For an exemplary smart-sensor system model, we show that quasi-periodic events that trigger activities in TD processes are handled accurately after the predictor has settled.
The paper illustrates the status quo of a research project for the development of a control system enabling CHP units for a demand-oriented electricity production by an intelligent management of the heat storage tank. Thereby the focus of the project is twofold. One is the compensation of the fluctuating power production by the renewable energies solar and wind. Secondly, a reduction of the load on the power grid is intended by better matching local electricity demand and production.
In detail, the general control strategy is outlined, the method utilized for forecasting heat and electricity demand is illustrated as well as a correlation method for the temperature distribution in the heat storage tank based on a Sigmoid function is proposed. Moreover, the simulation model for verification and optimization of the control system and the two field test sites for implementing and testing the system are introduced.
The current paper discusses the optimal choice of a filter time constant for filtering the steady state flux reference in an energy efficient control strategy for changing load torques. It is shown that by appropriately choosing the filter time constant as a fraction of the rotor time constant the instantaneous power losses after a load torque step can be significantly reduced compared to the standard case. The analysis for the appropriate choice of the filter time constant is based on a numerical study for three different induction motors with different rated powers.
In diesem Beitrag wird ein kapazitiver Low Power DC-DC Wandler mit 15 konfigurierbaren Übersetzungsverhältnissen, einem hohen Eingangsspannungsbereich von 5 V bis 20 V und einer konstanten Ausgangsspannung von 5 V vorgestellt. Bei einer Ausgangsleistung von 5 mW wird ein maximaler Wirkungsgrad von 81% erreicht. Die Implementierung erfolgt in einem 350 nm Hochvolt-CMOS-Prozess. Während es für niedrige Eingangsspannungen eine Vielzahl an Topologien und Konzepten gibt, wurden vollintegrierte SC-Wandler für höhere Eingangsspannungen (> 8 V) bisher nur wenig untersucht. Höhere Spannungen erfordern den Einsatz von Hochvolttransistoren und eine aufwändigere Ansteuerung. Um über einen weiteren Eingangsspannungsbereicht mit hoher Genauigkeit und hohem Wirkungsgrad zu wandeln, erweist sich die Topologie des rekursiven Switched-Capacitor Wandlers (RSC Wandler) als vorteilhaft. In der vorliegenden 4-Bit Implementierung ist der RSC Wandler aus N = 4 2:1 Serien-Parallel Wandler-Zellen aufgebaut. Durch verschiedene Anordnung der einzelnen Zellen können 2ᴺ -1 = 15 Wandlungsverhältnisse realisiert werden. Mittels Rekursion werden in jedem Wandlungsverhältnis alle Kapazitäten genutzt, wodurch die Stromfähigkeit und der Wirkungsgrad des Wandlers deutlich verbessert werden. Einheitliche 2:1 Wandler-Zellen ermöglichen einen modularen Aufbau des Layouts.
Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum conversion ratio are limited by the duty cycle of a PWM signal. In DCDC converters, a sawtooth generator is the fundamental circuit block to generate the PWM signal. The presented PWM generator is based on two parallel, fully interleaved PWM generator stages, each containing an integrator based sawtooth generator and two 3-stage highspeed comparators. A digital multiplexing of the PWM signals of each stage eliminates the dependency of the minimum on-time on the large reset times of the sawtooth ramps. A separation of the references of the PWM comparators in both stage allows to configure the PWM generator for a DCDC converter operating in fixed frequency or in constant on-time mode, which requires an operation in a wide frequency range. The PWM generator was fabricated in an 180 nm HV BiCMOS technology, as part of a DCDC converter. Measurements confirm minimum possible ontime pulses as short as 2 ns and thus allows switching frequencies of DCDC converters of >50 MHz at small duty cycle of <10%. At moderate duty cycles switching frequencies up to 100 MHz are possible.
This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125 ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30%by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2A load. The peak efficiency is 81 %.
Galvanic isolated gate drivers require a control signal as well as energy transmission from the control side (lowside) to the driver side (high-side). An additional backward signal transmission is preferred for error signals, status information, etc. This is often realized by means of several transformers or opto-couplers. Decreasing the number of isolation elements results in lower cost and a higher degree of miniaturization. This work presents a gate driver with bidirectional signal transmission and energy transfer via one single transformer. The key concept proposed in this paper is to combine bootstrapping to deliver the main gate charge for the driven power switch with additional energy transfer via the signal transformer. This paper also presents a very efficient combination of energy transfer to two high-side supply rails with back channel amplitude modulation. This way an isolated gate driver can be implemented that allows 100% pulse-width modulation (PWM) duty cycle at low complexity and system cost. The proposed high-side driver IC with integrated power supply, modulation and demodulation circuits was manufactured in a 180nm high-voltage BiCMOS technology. Measurements confirm the concept of bidirectional signal transmission with a 1MBit/s amplitude modulation, 10/20MHz frequency modulation and a maximum power transmission of 14mW via the transformer.
There is a growing need for motor drives with improved EMC in various automotive and industrial applications. An often referenced approach to reduce EME is to change the shape of the switching signal to reduce the EMI caused by the voltage and current transitions. This requires very precise gate control of the power MOSFET to achive better switching behaviour and lower EME without a major increase in switching losses. In order to find an optimal trade-off, this work utilizes a monolithic current mode gate driver with a variable output current that can be changed within 10ns. With this driver, measurements with different gate current profiles were taken. The di/dt transition was confirmed to be as important as the dv/dt transition in the power MOSFET. As a result of the improved switching behavior the emissions were reduced by up to 20dB between 7MHz and 60MHz with a switching loss that is 52% lower than with a constantly low gate current.
A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching
(2015)
Fast switching power supplies allow to reduce the size and cost of external passive components. However, the capacitive switching losses of the power stage will increase and become the dominant part of the total losses. Therefore, resonant topologies are the known key to reduce the losses of the power stage. A power switch with an additional resonant circuit can be turned on under soft-switching conditions, ideally with zero-voltage-switching (ZVS). As conventional resonant converts are only efficient for a constant load, this paper presents a predictive regulation loop to approach soft-switching conditions under varying load and component tolerances. A sample and hold based detection circuit is utilized to control the turn-on of the power switch by a digital regulation. The proposed design was fabricated in a 180 nm high-voltage BiCMOS technology. The efficiency of the converter was measured to be increased by up to 16 % vs. worst case timing and by 13 % compared to a conventional hard-switching buck converter at 20 V input voltage and at approximately 8 MHz switching frequency.
We presented our robot framework and our efforts to make face analysis more robust towards self-occlusion caused by head pose. By using a lightweight linear fitting algorithm, we are able to obtain 3D models of human faces in real-time. The combination of adaptive tracking and 3D face modelling for the analysis of human faces is used as a basis for further research on human-machine interaction on our SCITOS robot platform.
In practice, the use of layout PCells for analog IC design has not advanced beyond primitive devices and simple modules. This paper introduces a Constraint-Administered PCell-Applying Blocklevel Layout Engine (CAPABLE) which permits PCells to access their context, thus enabling a true "bottom-up" development of complex parameterized modules. These modules are integrated into the design flow with design constraints and applied by an execution cockpit via an automatically built layout script. The practical purpose of CAPABLE is to easily generate full-custom block layouts for given schematic circuits. Perspectively, our results inspire a whole new conception of PCells that can not only act (on demand), but also react (to environmental changes) and interact (with each other).
A generic, knowledge-based method for automatic topology selection of analog circuits in a predefined analog reuse library is presented in this paper on the OTA (Operational Transconductance Amplifier) example. Analog circuits of a given circuit class are classified in a topology tree, where each node represents a specific topology. Child nodes evolve from their parent nodes by an enhancement of the parent node’s topological structure. Topology selection is performed by a depth first-search in the topology tree starting at the root node, thus checking topologies of increasing complexity. The decisions at each node are based on solving equations or – if this is not possible – on simulations. The search ends at the first (and thus the simplest) topology which can meet the specification after an adequate circuit sizing. The advantages of the generic, tree based topology selection method presented in this paper are shown in comparison to a pool selection method and to heuristic approaches. The selection is based on an accomplished chip investigation.
Eine neue Methode zur Berechnung von Temperaturen in Bonddrähten umgeben von einem endlichen Mold wird vorgestellt. Sie ist schneller als die übliche Finite Elemente-Methode (FEM), während sie vergleichbare Resultate produziert. Für manche Parameter funktioniert unsere Methode, während die FEM-Methode versagt. Der Algorithmus ist im sogenannten Bondrechner implementiert, der eine leicht zu benutzende Oberfläche für Designer von mikroelektronischen Systemen bereitstellt. Seine Anwendung hat das Potential, die Zuverlässigkeit von Bonddrähten zu verbessern. Ein nichtidealer Parameter für den Wärmetransfer vom Bonddraht zum Mold-Package wurde ebenfalls berücksichtigt. Dieser Parameter ändert sich wahrscheinlich unter Alterseinflüssen und ist daher sehr wichtig für Zuverlässigkeits-Schätzungen. In unserer Methode wird die Wechselwirkung von Nachbardrähten ebenfalls berücksichtigt. Diese wird immer wichtiger, weil der Durchmesser und der wechselseitige Abstand der Bonddrähte sich verringert, wegen der fortschreitenden Miniaturisierung der Chip-Verpackungen. Unser Programm kann ebenfalls Temperaturen für transiente Ströme berechnen und den Strom berechnen, der zu einer gegebenen Maximaltemperatur gehört.
Es wird ein hochintegrierter Gatetreiber für 600V-Anwendungen mit einer galvanischen Isolation zwischen der Ansteuerelektronik und der Treiberseite vorgestellt. Eine Besonderheit ist die bidirektionale Signalübertragung und die Energieversorgung über einen einzigen Transformator. Die Treiberansteuersignale werden mittels 10/20 MHz Frequenzmodulation übertragen. Die Signalrückübertragung ist in Form einer 1Mbit/s Amplitudenmodulation realisiert. Die Energieübertragung über den Transformator erlaubt ein dauerhaftes Einschalten des Treibers. Der Energiebedarf während des Schaltvorgangs wird hauptsächlich durch eine Bootstrapschaltung bereitgestellt. Eine weitere Besonderheit ist die Verwendung einer flächeneffizienten Integration einer NMOS Treiberausgangsstufe. Der Gatetreiber wurde in einer 180nm Hochvolt-BiCMOS-Technologie hergestellt. Messungen bestätigen die Funktion des Treibers.
Large power semiconductors are complex structures, their metallization usually containing many thousands of contacts or vias. Because of this, detailed FEM simulations of the whole device are nowadays not possible because of excessive simulation time.
This paper introduces a simulation approach which allows quick identification of critical regions with respect to lifetime by a simplified simulation. For this, the complex layers are replaced by a much simpler equivalent layer, allowing a simulation of the whole device even including its package. In a second step, precise simulations taking all details of the structure into account are carried out, but only for the critical regions of interest. Thus, this approach gives detailed results where required with consideration of the whole structure including packaging. Further, the simulation time requirements are very moderate.
Innovative Antriebstechnik muss die aktuellen Anforderungen und die spezifischen Anwenderwünsche mit den verfügbaren technologischen Möglichkeiten in hocheffiziente Lösungen umsetzen. Dazu müssen Elektronik, Software und Mechanik von der Berechnung bis zur Ausführung passgenau integriert und optimiert sein, um auch die heutigen ökonomischen und ökologischen Ansprüche an moderne Antriebe zu erfüllen.
This paper describes the design and outcomes of an experimental study that addresses stock-and-flow-failure from a cognitive perspective. It is based on the assumption that holistic (global) and analytic (local) processing are important cognitive mechanisms underlying the ability to infer the behavior of dynamic systems. In a stock-and-flow task that is structurally equivalent to the department store task, we varied the format in which participants are primed to think about an environmental system, in particular whether they are primed to concentrate on lower-level (local) or higher-level (global) system elements. 148 psychology, geography and business students participated in our study. Students’ answers support our hypothesis that global processing increases participants’ ability to infer the overall system behavior. The beneficial influence of global presentation is even stronger when data are presented numerically rather than in the form of a graph. Our results suggest presenting complex dynamic systems in a way that facilitates global processing. This is particularly important as policy-designers and decision makers deal with complex issues in their everyday and professional life.
SF-failure, the inability of people to correctly determine the behavior of simple stock and flow structures is subject of a long research stream. Reasons for SF-failure can be attributed to different reasons, one of them being lacking domain specific experience, thus familiarity with the problem context. In this article we present a continuation of an experiment to examine the role of educational background in SF-performance. We base the question set on the Bathtub Dynamics tasks introduced by Booth Sweeney and Sterman (2000) and vary the cover stories. In this paper we describe how we developed and tested a new cover story for the engineering domain and implemented the recommendations from a prior study. We test three sets of questions with engineering students which enables us to compare the results to a previous study in which we tested the questions with business students. Results mainly support our hypothesis that context familiarity increases SF-performance. With our findings we further develop the methodology of the research on SF-failure.
An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters
(2015)
The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm2. The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm2. This exceeds prior art by a factor of 11.
Der elektrische Wirkungsgrad stellt eines der wichtigsten Bewertungskriterien für BHKW dar, da über diese Größe ausgedrückt wird, wie viel des Wertproduktes „elektrische Energie“ bezogen auf die eingesetzte oder aufzuwendende Brennstoffenergie produziert werden kann. Ein hoher elektrischer Wirkungsgrad ist somit gleichbedeutend mit hohen Erlösen aus dem Verkauf der erzeugten elektrischen Energie und damit eine grundlegende Voraussetzung für einen wirtschaftlichen Betrieb eines BHKWs. Folglich sind die Hersteller von BHKW bestrebt, den elektrischen Wirkungsgrad ihrer Geräte kontinuierlich zu verbessern und nach oben zu treiben. Dieses Bemühen zeigt sich eindrucksvoll an der Entwicklung der mechanischen Effizienz von Gasmotoren der Firma GE Jenbacher. Während mit Motoren der Baureihe 6 im Leistungsbereich 1,8 – 4,4 MWel im Jahr 1988 eine mechanische Effizienz von 34% erreichbar war, liegt dieser Wert mittlerweile bei etwa 47,5%. Diese enorme Steigerung konnte im Wesentlichen durch eine Erhöhung des mittleren effektiven Zylinderarbeitsdrucks von etwa 10 bar im Jahr 1988 auf derzeit 24 bar erzielt werden. Dabei hilft der Magerbetrieb, der gleichzeitig ein Zurückdrängen der NOx-Emissionen bewirkt, die Klopfgrenze zu höheren Drücken hin zu verschieben. Eine sichere Zündung des Gas-Luft-Gemisches wird durch die Vorkammerzündung erreicht.
An improved gate drive circuit is provided for a power device, such as a transistor. Tue gate driver circuit may in -clude: a current control circuit; a first secondary current source that is used to control the switching transient during turn off of the power transistor and a second secondary current source that is used to control the switching transient during turn on of the power transistor. In operation, the current control circuit operates, during turn on ofthe power transistor, to source a gate drive current to a control node ofthe power transistor and, during turn off ofthe power transistor, to sink a gate drive current from the control node of the power transistor. The first and second secondary current sources adjust the gate drive current to control the voltage or current rate of change and thereby the overshoot during the switching transient.
In dieser Arbeit wird eine optimierte Bandgap-Referenz zur Erzeugung einer temperaturstabilen Spannung und eines Referenzstroms vorgestellt. Für Low-Power-Anwendungen wurde die Bandgap-Referenz, basierend auf der Brokaw-Zelle, mit minimaler Stromaufnahme und optimierter Chipfläche durch Multi-Emitter-Layout der Bipolartransistoren implementiert. Zusätzliches Merkmal ist ein verbreiteter Versorgungsspannungsbereich von 2,5 bis 5,5 V. Simulationen zeigen, dass eine stabile Ausgangsspannung von 1,218 V und ein Referenzstrom von 1,997 μA realisiert wird. Im Temperaturbereich -40 °C … 50 °C sowie dem gesamten Bereich der Versorgungsspannung beträgt die Genauigkeit der Referenzspannung ± 0,04 % mit einer Gesamtstromaufnahme zwischen 3,5 und 10 μA. Es wird eine Temperaturdrift von 2,18 ppm/K erreicht. Durch das elektronische Trimmen von Widerständen wird der Offset der Ausgangsspannung, bedingt durch Herstellungstoleranzen, auf ±3,5 mV justiert. Die Referenz wird in einer 0,18 μm BiCMOS-Technologie implementiert.
Die Nachfrage nach kompakten Spannungsversorgungen ist in den letzten Jahren stark gestiegen. Vor allem im Bereich der mobilen Geräte wachsen die Anforderung an die Spannungsversorgung hinsichtlich Bauvolumen und Batterielaufzeit. Für die Vollintegration von DC-DC- Wandlern als „Power Supply on Chip“ ist der SC-Wandler (Switched-Capacitor-Wandler) besonders geeignet. Insbesondere für Low-Power-Anwendungen im Bereich 10 mW kann ein SC-Wandler sehr gut, ohne externe Bauelemente, integriert werden. Während es für niedrige Eingangsspannungen (bis zu 5 V) eine Vielzahl an Topologien und Konzepten gibt, wurden SC-Wandler für höhere Eingangsspannungen (> 8 V) bisher nur wenig untersucht. Dieser Beitrag untersucht die wichtigsten Grundlagen für SC-Wandler mit Schwerpunkt auf hoher und zugleich variabler Eingangsspannung im Bereich 5 - 20 V. Am Beispiel eines Multi-Ratio-Wandlers (Wandler mit mehreren Übersetzungsverhältnissen), dem rekursiven SC-Wandler (RSC- Wandler), werden die Anforderungen eines SC- Wandler für hohe Eingangsspannungen herausgearbeitet und diskutiert.
A millimeter-wave power amplifier concept in an advanced silicon germanium (SiGe) BiCMOS technology is presented. The goal of the concept is to investigate the impact of physical limitations of the used heterojunction bipolar transistors (HBT) on the performance of a 77 GHz power amplifier. High current behavior, collectorbase breakdown and transistor saturation can be forced with the presented design. The power amplifier is manufactured in an advanced SiGe BiCMOS technology at Infineon Technologies AG with a maximum transit frequency fT of around 250 GHz for npn HBT’s [1]. The simulation results of the power amplifier show a saturated output power of 16 dBm at a power added efficiency of 13%. The test chip is designed for a supply voltage of 3.3 V and requires a chip size of 1.448 x 0.930 mm².
Durch schnell schaltende Leistungsendstufen werden durch kapazitive Umladeströme Störungen ins Substrat und in empfindliche Schaltungselemente eingekoppelt, die dort zur Störung der Funktion führen können. In dieser Arbeit werden Substratstrukturen zur gezielten Ableitung dieser Störungen vorgestellt und ihre Wirksamkeit mit Hilfe von Device Simulation evaluiert. Ohne Ableitstrukturen kann eine Potentialanhebung des Substrats bis zu 20 V entstehen. Die Untersuchungen belegen, dass die Potentialanhebung durch p-Typ Guard-Ringe um 75 %, durch leitende Trenches um 88 % sowie durch Rückseitenmetallisierung um nahezu 100 % reduziert werden kann.
Im Bereich integrierter Schaltungen (ICs) für die Fahrzeugelektronik ist in den letzten Jahren ein Trend zum Einsatz komplexer Mixed-Signal-Komponenten erkennbar. Dies führt dazu, dass ein altes Problem zunehmend in den Fokus der EDA-Entwickler rückt: Während der digitale Entwurfsfluss hoch automatisiert ist, findet der Entwurf analoger Komponenten überwiegend in einem manuellen, zeitaufwändigen und interaktiven Entwurfsstil statt. Die folgende Arbeit beschreibt ein Konzept, diesen Mangel mit Hilfe eines durchgängigen analogen Entwurfsflusses unter Verwendung so genannter Modul-Generatoren zu mildern. Der vorgestellte Ansatz zur Erzeugung von Schaltkreis-Automatismen berücksichtigt die implizite Nutzung von Erfahrungswissen des Designers, bietet eine volle Topologie-Flexibilität und steigert die Wiederverwendung („re-use“) gängiger Schaltungstopologien. Die erreichten Zwischenergebnisse lassen einen erheblichen Nutzen erkennen und zeigen das Potenzial sogenannter „Parametrisierter Schaltkreise“ auf, den Automatisierungsgrad des analogen Schaltungsentwurfs zu steigern.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
Bootstrap circuits are mainly used for supplying a gate driver circuit to provide the gate overdrive voltage for a high-side NMOS transistor. The required charge has to be provided by a bootstrap capacitor which is often too large for integration if an acceptable voltage dip at the capacitor has to be guaranteed. Three options of an area efficient bootstrap circuit for a high side driver with an output stage of two NMOS transistors are proposed. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and connected when the gate driver turns on. A high voltage swing at the second capacitor leads to a high charge allocation. Both bootstrap capacitors require up to 70% less area compared to a conventional bootstrap circuit. This enables compact power management systems with fewer discrete components and smaller die size. A calculation guideline for optimum bootstrap capacitor sizing is given. The circuit was manufactured in a 180nm high-voltage BiCMOS technology as part of a high-voltage gate driver. Measurements confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit including two stacked 75.8pF and 18.9pF capacitors results in a voltage dip lower than 1V. This matches well with the theory of the calculation guideline.
In this paper, research projects with 30 meter balanced cabling and data rates up to 25 Gbps over one single pair are described. The project aim is to achieve 100 Gbps via a four pair balanced cabling channel. In the following, spectral characteristics of the used prototype twisted pair are presented. Therefore, the insertion loss of the single cable in comparison to the insertion loss of the cable in combination with an equalizing amplifier, as well as the group delay of the cable and the cable connected to the equalizing amplifier is shown. Furthermore, a carrierless Pulse Amplitude Modulation with 32 different levels (PAM-32) as an approach for a possible line encoding is presented. Finally, research measurements of the data transmission with a data rate up to 25 Gbps via shielded twisted pair is shown.
While digital IC design is highly automated, analog circuits are still handcrafted in a time-consuming, manual fashion today. This paper introduces a novel Parameterized Circuit Description Scheme (PCDS) for the development of procedural analog schematic generators as parameterized circuits. Circuit designers themselves can use PCDS to create circuit automatisms which capture valuable expert knowledge, offer full topological flexibility, and enhance the re-use of well-established topologies. The generic PCDS concept has been successfully implemented and employed to create parameterized circuits for a broad range of use cases. The achieved results demonstrate the efficiency of our PCDS approach and the potential of parameterized circuits to increase automation in circuit design, also to benefit physical design by promoting the common schematic-driven-layout flow, and to enhance the applicability of circuit synthesis approaches.
This paper presents the design and simulation processes of an Equiangular Spiral Antenna for the extremely high frequencies between 65 GHz and 170 GHz. A new approach for the analysis of the antenna’s electrical parameters is described. This approach is based on formalism proposed by Rumsey to determine the EM field produced by an equiangular spiral antenna. Analytical expressions of the electrical parameters such as the gain or the directivity are then calculated using well sustained mathematical approximations. The comparison of obtained results with those from numerical integration methods shows a good agreement.
This paper presents a new broadband antenna for satellite communications. It describes the procedure involved in the design of a microstrip antenna array and its multi-level passive feed network that together yield circular polarization and the necessary gain to be used in an earth-satellite link. The designed antenna is notable for its large bandwidth, circular polarization, high gain and small dimensions.
IGBT modules with anti-parallel FWDs are widely used in inductive load switching power applications, such as motor drive applications. Nowadays there is a continuous effort to increase the efficiency of such systems by decreasing their switching losses. This paper addresses the problems arising in the turn-on process of an IGBT working in hard-switching conditions. A method is proposed which achieves – contrary to most other approaches – a high switching speed and, at the same time, a low peak reverse-recovery current. This is done by applying an improved gate current waveform that is briefly lowered during the turn-on process. The proposed method achieves low switching losses. Its effectiveness is demonstrated by experimental results with IGBT modules for 600V and 1200V.
Today 40 Gbps is in development at IEEE 802.3bq over four pair balanced cabling. In this paper, we describe a transmission experiment of 25 Gbps enabling either a single pair transmission of 25 Gbps over a 30 meter balanced cabling channel, or a 100 Gbps transmission via a four-pair balanced channel. A scalable matrix modeling tool is introduced which allows the prediction of transmission characteristics of a channel taking mode conversion into account . We applied this tool to characterize PCB-channels including the magnetics and PCB for a four-pair 100 Gbps transmission. We evaluated prototype cables and connecting hardware for frequencies up to 2 GHz and beyond. Finally we investigated possible line encoding schemes and provide measurement results of a transmission over 30 m with a data rate of 25 Gbps per twisted pair.
Die Hochschule Reutlingen hat eine vergleichende Untersuchung an Spannfuttern für Schaftfräser vorgenommen. Fazit: Die Steifigkeit einer Aufnahme hat einen stärkeren Einfluss auf das Schwingverhalten als das Dämpfungsvermögen.
Das dynamische Verhalten von Werkzeugmaschinen besitzt entscheidenden Einfluss auf die Bearbeitungsergebnisse. Zusammen mit dem Eigenverhalten der Maschine und dem Werkstück ergibt dies die für die Bearbeitungsgenauigkeit entscheidende statische Steifigkeit und die dynamische Nachgiebigkeit. Im Folgenden wird das Zusammenspiel dieser Komponenten im System näher dargestellt.
Prior studies ascribed people’s poor performance in dealing with basic systems concepts to different causes. While results indicate that, among other things, domain specific experience and familiarity with the problem context play a role in this stock-flow-(SF-)performance, this has not yet been fully clarified. In this article, we present an experiment that examines the role of educational background in SF-performance. We hypothesize that SF-performance increases when the problem context is embedded in the problem solver’s knowledge domain, indicated by educational background. Using the square wave pattern and the sawtooth pattern tasks from the initial study by Booth Sweeney and Sterman (2000), we design two additional cover stories for the former, the Vehicle story from the engineering domain and the Application story from the business domain, next to the original Bathtub story. We then test the three sets of questions on business students. Results mainly support our hypothesis. Interestingly, participants even do better on a more complex behavioral pattern from their knowledge domain than on a simpler pattern from more distant domains. Although these findings have to be confirmed by further studies, they contribute both to the methodology of future surveys and the context familiarity discussion.