621 Angewandte Physik
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Besides the optimisation of the car, energy-efficiency and safety can also be increased by optimising the driving behaviour. Based on this fact, a driving system is in development whose goal is to educate the driver in energy efficient and safe driving. It monitors the driver, the car and the environment and gives energy-efficiency and safety relevant recommendations. However, the driving system tries not to distract or bother the driver by giving recommendations for example during stressful driving situations or when the driver is not interested in that recommendation. Therefore, the driving system monitors the stress level of the driver as well as the reaction of the driver to a given recommendation and decideswhether to give a recommendation or not. This allows to suppress recommendations when needed and, thus, to increase the road safety and the user acceptance of
the driving system.
In dieser Arbeit wird eine optimierte Bandgap-Referenz zur Erzeugung einer temperaturstabilen Spannung und eines Referenzstroms vorgestellt. Für Low-Power-Anwendungen wurde die Bandgap-Referenz, basierend auf der Brokaw-Zelle, mit minimaler Stromaufnahme und optimierter Chipfläche durch Multi-Emitter-Layout der Bipolartransistoren implementiert. Zusätzliches Merkmal ist ein verbreiteter Versorgungsspannungsbereich von 2,5 bis 5,5 V. Simulationen zeigen, dass eine stabile Ausgangsspannung von 1,218 V und ein Referenzstrom von 1,997 μA realisiert wird. Im Temperaturbereich -40 °C … 50 °C sowie dem gesamten Bereich der Versorgungsspannung beträgt die Genauigkeit der Referenzspannung ± 0,04 % mit einer Gesamtstromaufnahme zwischen 3,5 und 10 μA. Es wird eine Temperaturdrift von 2,18 ppm/K erreicht. Durch das elektronische Trimmen von Widerständen wird der Offset der Ausgangsspannung, bedingt durch Herstellungstoleranzen, auf ±3,5 mV justiert. Die Referenz wird in einer 0,18 μm BiCMOS-Technologie implementiert.
A millimeter-wave power amplifier concept in an advanced silicon germanium (SiGe) BiCMOS technology is presented. The goal of the concept is to investigate the impact of physical limitations of the used heterojunction bipolar transistors (HBT) on the performance of a 77 GHz power amplifier. High current behavior, collectorbase breakdown and transistor saturation can be forced with the presented design. The power amplifier is manufactured in an advanced SiGe BiCMOS technology at Infineon Technologies AG with a maximum transit frequency fT of around 250 GHz for npn HBT’s [1]. The simulation results of the power amplifier show a saturated output power of 16 dBm at a power added efficiency of 13%. The test chip is designed for a supply voltage of 3.3 V and requires a chip size of 1.448 x 0.930 mm².
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum conversion ratio are limited by the duty cycle of a PWM signal. In DCDC converters, a sawtooth generator is the fundamental circuit block to generate the PWM signal. The presented PWM generator is based on two parallel, fully interleaved PWM generator stages, each containing an integrator based sawtooth generator and two 3-stage highspeed comparators. A digital multiplexing of the PWM signals of each stage eliminates the dependency of the minimum on-time on the large reset times of the sawtooth ramps. A separation of the references of the PWM comparators in both stage allows to configure the PWM generator for a DCDC converter operating in fixed frequency or in constant on-time mode, which requires an operation in a wide frequency range. The PWM generator was fabricated in an 180 nm HV BiCMOS technology, as part of a DCDC converter. Measurements confirm minimum possible ontime pulses as short as 2 ns and thus allows switching frequencies of DCDC converters of >50 MHz at small duty cycle of <10%. At moderate duty cycles switching frequencies up to 100 MHz are possible.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125 ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30%by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2A load. The peak efficiency is 81 %.
A lot of people need help in their daily life to wash, select and manage their clothing. The goal of this work is to design an assistant system (eKlarA) to support the user by giving recommendations to choose the clothing combinations, to find the clothing and to wash the clothing. The idea behind eKlarA is to generate a system that uses sensors to identify the clothing and their state in the clothing cycle. The clothing cycle consists of the stations: closets, laundry basket and washing machine in one or several places. The system uses the information about the clothing, weather and calendar to support the user in the different steps of the clothing cycle. The first prototype of this system has been developed and tested. The test results are presented in this work.
The superior electrical and thermal properties of silicon carbide (SiC) allow further shrinking of the active area of future power semiconductor devices. A lower boundary of the die size can be obtained from the thermal impedance required to withstand the high power dissipation during a short-circuit event. However, this implies that the power distribution is homogeneous and that no current filamentation has to be considered. Therefore, this work investigates this assumption by evaluating the stability of a SiC-MOSFET over a wide range of operation conditions by measurements up to destruction, thermal simulations, and high-temperature characterization.