The 10 most recently published documents
Eine Herausforderung im Rahmen aufsichtsrechtlicher Bankenprüfungen, regelmäßiger Validierungen und interner Revisionsprüfungen ist nach Ansicht der beiden Autoren die Prognosefähigkeit eines Ratingverfahrens als objektiv und belastbar zu beurteilen. In ihrem Beitrag untersuchen sie deshalb die unterschiedlichen Vor- und Nachteile maschineller Lernverfahren für die Kreditrisikomessung gegenüber den klassischen Ratingverfahren. Diese seien ein pragmatisches Werkzeug für Validierungseinheiten und interne Revision. Nach genauer Überprüfung der Verfahren kommen sie zu dem Schluss, es sei nicht mehr eine Frage, ob, sondern vielmehr wann die maschinellen Lernverfahren zu einem selbstverständlichen Bestandteil der Kreditrisikomessung werden.
The hotspot detection has received much attention in the recent years due to a substantial mismatch between lithography wavelength and semiconductor technology feature size. This mismatch causes diffraction when transferring the layout from design onto a silicon wafer. As a result, open or short circuits (i.e. lithography hotspots) are more likely to be produced. Additionally, increasing numbers of semiconductors devices on a wafer required more time for the lithography hotspot detection analysis. In this work, we propose a fast and accurate solution based on novel artificial neural network (ANN) architecture for precise lithography hotspot detection using a convolution neural network (CNN) adopting a state of-the-art technique. The experimental results showed that the proposed model gained accuracy improvement over current state-of-theart approaches. The final code has been made publicly available.
Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM verification to robust (pro-active) EM aware design - where the circuit layout is designed with individual EM-robust solutions - is urgently needed. This tutorial will give an overview of EM and its effects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its specific characteristics that can be affected during physical design. Examples of EM countermeasures which are applied in today’s commercial design flows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission proiles to obtain application-oriented current density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post layout EM verification towards an EM aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit’s reliability.
The very first International Workshop on Software-intensive Business: Start-ups, Ecosystems and Platforms (SiBW 2018) was held in Espoo (Greater Helsinki), Finland on December 3rd, 2018 – just a day before SLUSH 2018, the world’s biggest startup event. Thanks to the collaboration with the organizers of SLUSH, many of the software-intensive business researchers and practitioners took part also in this event.
The international workshop gathered together 35 registered attendees, from Sweden, Germany, Latvia, Finland, Italy and the Netherlands representing both academia as well as industry. The event itself was sponsored by VTT Technical Research Centre of Finland and the workshop was organized by the newly founded Software-intensive Business research community together with Software Startup Research Network (SSRN).
This research addresses the question of why employees use enterprise social networks (ESN). Against the background of technology acceptance research, we propose an extended unified theory of acceptance and use of technology (UTAUT) model, adapt it to an ESN context, and test our model against data from ESN users of large and medium-sized enterprises. We use partial least squares structural equation modeling to gain insights into the determinants of ESN use. This paper contributes to ESN acceptance research by evaluating a model containing determinants of ESN use. It also examines the effects of determinants on five different usage dimensions of ESN. The results reveal that facilitating conditions are the main driver of ESN use while the impact of intention to use is comparably small. Implications for theory and practice are discussed.
We present a dual active bridge topology suitable for wide voltage range applications covering all combinations of 200V to 600V on the input and 20V to 60V on the output with constant power of 1kW.We employ a stepped inductance scheme to adjust the effective inductance of the converter, thus extending the efficient operation range. Using a variable switching frequency between 35 kHz and 150 kHz with operation-point-dependent limits further increases the performance of the converter. A prototype was built and the proposed changes have been compared to a fixed frequency, fixed inductance implementation. Measurements show a maximum loss reduction of 40 %, leading to a peak efficiency of 97% while maintaining constant output power over the entire working area.
Many GaN power transistors contain a PN junction between gate and the channel region close to the source. In order to maintain the on-state, current must continuously be supplied to the junction. Therefore, the commonly recommended approach uses a gate bias voltage of 12V to compensate the Miller current through a boost circuit. For the same purpose, a novel gate driving method based on an inductive feed forward has been presented. With this, stable turn-on can be achieved even for a bias voltage of only 5V. The effectiveness of this concept is demonstrated by double pulse measurements, switching currents up to 27A and a voltage of 400V. For both approaches a compact design with low source inductance is characterized. In addition to the significant reduction of the gate bias voltage and peak gate current, the new approach reduces the switching losses for load currents >23 A.
