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The loss contribution of a 2.3kW synchronous GaN-HEMT boost converter for an input voltage of 250V and an output voltage of 500V was analyzed. A simulation model which consists of two parts is introduced. First, a physics-based model is used to determine the switching losses. Then, a system simulation is applied to calculate the losses of the specific elements. This approach allows a fast and accurate system evaluation as required for further system optimization.
In this work, a hard- and a zero-voltage turn-on switching converter are compared. Measurements were performed to verify the simulation model, showing a good agreement. A peak efficiency of 99% was achieved for an output power of 1.4kW. Even with an output power above 400W, it was possible to obtain a system efficiency exceeding 98 %.
This paper presents a compact 3 kW bidirectional GaN-HEMT DC/DC converter for 360V to 400-500 V. A very high efficiency has been reached by applying a zero voltage turn-on in conjunction with a negative gate-source voltage, even though normally-off HEMTs are used. Further improvements were achieved by adapting the switching frequency to the load current and output voltage, as will be explained by means of the loss contribution of the specific elements for a constant and an adaptive switching frequency. Measurements have shown a high converter efficiency exceeding 99% over a wide output power range of up to 3 kW.
A gate driver approach is presented for the reduction of turn-on losses in hard switching applications. A significant turn-on loss reduction of up to 55% has been observed for SiCMOSFETs. The gate driver approach uses a transformer which couples energy from the power path back into the gate path during switching events, providing increased gate driver current and thereby faster switching speed.
The gate driver approach was tested on a boost converter running at a switching frequency up to 300 kHz. With an input voltage of 300V and an output voltage of 600V, it was possible to reduce the converter losses by 8% at full load. Moreover, the output power range could be extended by 23% (from 2.75kW to 3.4 kW) due to the reduction of the turn-on losses.
Many GaN power transistors contain a PN junction between gate and the channel region close to the source. In order to maintain the on-state, current must continuously be supplied to the junction. Therefore, the commonly recommended approach uses a gate bias voltage of 12V to compensate the Miller current through a boost circuit. For the same purpose, a novel gate driving method based on an inductive feed forward has been presented. With this, stable turn-on can be achieved even for a bias voltage of only 5V. The effectiveness of this concept is demonstrated by double pulse measurements, switching currents up to 27A and a voltage of 400V. For both approaches a compact design with low source inductance is characterized. In addition to the significant reduction of the gate bias voltage and peak gate current, the new approach reduces the switching losses for load currents >23 A.
A novel gate driving approach to balance the transient current of parallel-connected GaN-HEMTs
(2018)
To enable higher current handling capability of GaN-based DC/DC converters, devices have to be used in parallel. However, their switching times differ, especially if their threshold voltages are not identical, which causes unbalanced device current. This paper focuses on the homogeneous distribution of turn-on switching losses of GaN-HEMTs connected in parallel. By applying a new gate driver concept, the transient current is distributed evenly. The effectiveness of this concept is demonstrated by double pulse measurements, for switching currents up to 45A and a voltage of 400V. A uniform current distribution is achieved, including a reduction of the turn-on losses by 50% compared to a conventional setup.
Improved inductive feed-forward for fast turn-on of power semiconductors during hard switching
(2019)
A transformer is used to increase the gate voltage during turn-on, thus reducing the necessary bias voltage of the gate driver. Counteracting the voltage dependency of the gate capacitance of high-voltage power devices, faster transitions are possible. The additional transformer only slighly increases the over-voltage during turn-off.
Novel design for a coreless printed circuit board transformer realizing high bandwidth and coupling
(2019)
Rogowski coils offer galvanic isolation and can measure alternating currents with a high bandwidth. Coreless printed circuit board (PCB) transformers have been used as an alternative to limit the additional stray inductance if a Rogowski coil can not be attached to the circuit. A new PCB transformer layout is proposed to reduce cost, decrease additional stray inductance, increase the bandwidth of current measurements and simplify the integration into existing designs.
This paper investigates the electrothermal stability and the predominant defect mechanism of a Schottky gate AlGaN/GaN HEMT. Calibrated 3-D electrothermal simulations are performed using a simple semiempirical dc model, which is verified against high-temperature measurements up to 440°C. To determine the thermal limits of the safe operating area, measurements up to destruction are conducted at different operating points. The predominant failure mechanism is identified to be hot-spot formation and subsequent thermal runaway, induced by large drain–gate leakage currents that occur at high temperatures. The simulation results and the high temperature measurements confirm the observed failure patterns.
Advanced power semiconductors such as DMOS transistors are key components of modern power electronic systems. Recent discrete and integrated DMOS technologies have very low area-specific on-state resistances so that devices with small sizes can be chosen. However, their power dissipation can sometimes be large, for example in fault conditions, causing the device temperature to rise significantly. This can lead to excessive temperatures, reduced lifetime, and possibly even thermal runaway and subsequent destruction. Therefore, it is required to ensure already in the design phase that the temperature always remains in an acceptable range. This paper will show how self-heating in DMOS transistors can be experimentally determined with high accuracy. Further, it will be discussed how numerical electrothermal simulations can be carried out efficiently, allowing the accurate assessment of self-heating within a few minutes. The presented approach has been successfully verified experimentally for device temperatures exceeding 500 ◦C up to the onset of thermal runaway.
DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures, which can lead to device failure and reduced lifetime. Hence, it must be ensured that the device temperature does not rise too much. For this, the influence of the on-chip metallization must be taken into account because of the good thermal conductivity and significant thermal capacitance of the metal layers on top of the active DMOS area. In this paper, test structures with different metal layers and vias configurations are presented that can be used to determine the influence of the onchip metallization on the temperature caused by self-heating. It will be shown how accurate results can be obtained to determine even the influence of small changes in the metallization. The measurement results are discussed and explained, showing how on-chip metallization helps to lower the device temperature. This is further supported by numerical simulations. The obtained insights are valuable for technology optimization, but are also useful for calibration of temperature simulators.