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An integrated synchronous buck converter with a high resolution dead time control for input voltages up to 48V and 10MHz switching frequency is presented. The benefit of an enhanced dead time control at light loads to enable zero voltage switching at both the high-side and low-side switch at low output load is studied. This way, compact multi-MHz DCDC converters can be implemented at high efficiency over a wide load current range. The concept also eliminates body diode forward conduction losses and minimizes reverse recovery losses. A dead time resolution of 125 ps is realized by an 8-bit differential delay chain. A further efficiency enhancement by soft switching at the high-side switch at light load is achieved with a voltage boost of the switching node by dead time control in forced continuous conduction mode. The monolithic converter is implemented in an 180nm high-voltage BiCMOS technology. At V IN = 48V, V OUT = 5V, 50mA load, 10MHz switching frequency and 500 nH output inductance, the efficiency is measured to be increased by 14.4% compared to a conventional predictive dead time control. A peak efficiency of 80.9% is achieved at 12V input.
In recent years, significant progress has been made on switched-capacitor DC-DC converters as they enable fully integrated on-chip power management. New converter topologies overcame the fixed input-to-output voltage limitation and achieved high efficiency at high power densities. SC converters are attractive to not only mobile handheld devices with small input and output voltages, but also for power conversion in IoE, industrial and automotive applications, etc. Such applications need to be capable of handling widely varying input voltages of more than 10V, which requires a large amount of conversion ratios. The goal is to achieve a fine granularity with the least number of flying capacitors. In [1] an SC converter was introduced that achieves these goals at low input voltage VIN ≤ 2.5V. [2] shows good efficiency up to VIN = 8V while its conversion ratio is restricted to ≤1/2 with a limited, non-equidistant number of conversion steps. A particular challenge arises with increasing input voltage as several loss mechanisms like parasitic bottom-plate losses and gate-charge losses of high-voltage transistors become of significant influence. High input voltages require supporting circuits like level shifters, auxiliary supply rails etc., which allocate additional area and add losses [2-5]. The combination of both increasing voltage and conversion ratios (VCR) lowers the efficiency and the achievable output power of SC converters. [3] and [5] use external capacitors to enable higher output power, especially for higher VIN. However, this is contradictory to the goal of a fully integrated power supply.
The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm². The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm². This exceeds prior art by a factor of 11.
A high-voltage replica based current sensor is presented, along with challenges and design techniques which are rarely discussed in literature so far. The performance is evaluated by detailed small signal and large signal analysis. By dedicated placing of high-voltage cascode devices, while keeping as many low-voltage devices as possible, a high gain-bandwidth product is achieved. A decoupling and biasing circuit is introduced which improves the response time of the current sensor at on/off transitions by a factor of five. The current sensor is implemented in a 180nm HV BiCMOS technology. The sensor achieves a DC loop gain of 83 dB and a gain-bandwidth product of 7 MHz. With the proposed techniques, the gain-bandwidth product is increased by a factor of six. The measurable current range is between 60mA and 1.5 A. The performance is demonstrated in a 500 kHz buck converter at an input voltage of 40V. The overall circuit concept is suitable for 100V and beyond, enabling high performance power management designs including switched mode power supplies and motor applications.
This article analyses and compares the performance of regulators in the fields of finance and sport, especially cycling. I hypothesize that the courses of crises or scandals is the best time to study the lessons of regulatory response. First, I take into account the differences in both finance and cycling by looking at the nature of the rules and institutions governing the field. Second, I estimate the attention effect on new regulation in response to crises or scandals. The interest of the paper is in the alignment of incentives to prevent regulatory capture and to ensure accountability and enforceability. The paper concludes that the differences hold important lessons that call for the reform of rules and institutions governing finance and cycling alike.
This paper presents a compact 3 kW bidirectional GaN-HEMT DC/DC converter for 360V to 400-500 V. A very high efficiency has been reached by applying a zero voltage turn-on in conjunction with a negative gate-source voltage, even though normally-off HEMTs are used. Further improvements were achieved by adapting the switching frequency to the load current and output voltage, as will be explained by means of the loss contribution of the specific elements for a constant and an adaptive switching frequency. Measurements have shown a high converter efficiency exceeding 99% over a wide output power range of up to 3 kW.
The financial crisis of 2007-2010 was probably one of the greatest, most lustrous black-swan events that people of our generation(s) will experience – and at its heart, it was a dynamic phenomenon. It is stated in the vision of the System Dynamics Society that we aspire to transform society by influencing decision-making. Yet, it seems as if system dynamics did not play any significant role in this crisis: we did not examine the markets, we did not provide insights to banks, and we did not warn governments or the people. In our presentation we describe the dynamics involved in a housing bubble, and describe what made the last one different. With the insights gained from this exercise we conclude that, from a system dynamics perspective, the dimension of the financial crisis of 2007-2009 was eminently foreseeable, which will lead us to pose the following question: where were we as a field while this crisis was unfolding, why were we not active players? We present a range of potential answers to this question, hoping to provoke some reflection… and maybe some (re)action.
3D morphable face models are a powerful tool in computer vision. They consist of a PCA model of face shape and colour information and allow to reconstruct a 3D face from a single 2D image. 3D morphable face models are used for 3D head pose estimation, face analysis, face recognition, and, more recently, facial landmark detection and tracking. However, they are not as widely used as 2D methods - the process of building and using a 3D model is much more involved.
In this paper, we present the Surrey Face Model, a multi resolution 3D morphable model that we make available to the public for non-commercial purposes. The model contains different mesh resolution levels and landmark point annotations as well as metadata for texture remapping. Accompanying the model is a lightweight open-source C++ library designed with simplicity and ease of integration as its foremost goals. In addition to basic functionality, it contains pose estimation and face frontalisation algorithms. With the tools presented in this paper, we aim to close two gaps. First, by offering different model resolution levels and fast fitting functionality, we enable the use of a 3D Morphable Model in time-critical applications like tracking. Second, the software library makes it easy for the community to adopt the 3D morphable face model in their research, and it offers a public place for collaboration.