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Energy transfer kinetics in photosynthesis as an inspiration for improving organic solar cells
(2017)
Clues to designing highly efficient organic solar cells may lie in understanding the architecture of light harvesting systems and exciton energy transfer (EET) processes in very efficient photosynthetic organisms. Here, we compare the kinetics of excitation energy tunnelling from the intact phycobilisome (PBS) light harvesting antenna system to the reaction center in photosystem II in intact cells of the cyanobacterium Acaryochloris marina with the charge transfer after conversion of photons into photocurrent in vertically aligned carbon nanotube (va- CNT) organic solar cells with poly(3-hexyl)thiophene (P3HT) as the pigment. We find that the kinetics in electron hole creation following excitation at 600 nm in both PBS and va-CNT solar cells to be 450 and 500 fs, respectively. The EET process has a 3 and 14 ps pathway in the PBS, while in va-CNT solar cell devices, the charge trapping in the CNT takes 11 and 258 ps. We show that the main hindrance to efficiency of va CNT organic solar cells is the slow migration of the charges after exciton formation.
We present a topology of MIMO arrays of inductive antennas exhibiting inherent high crosstalk cancellation capabilities. A single layer PCB is etched into a 3-channels array of emitting/receiving antennas. Once coupled with another similar 3-channels emitter/receiver, we measured an Adjacent Channel Rejection Ratio (ACRR) as high as 70 dB from 150 Hz to 150 kHz. Another primitive device made out of copper wires wound around PVC tubes to form a 2-channels “non-contact slip-ring” exhibited 22 dB to 47 dB of ACRR up to 15MHz. In this paper we introduce the underlying theoretical model behind the crosstalk suppression capabilities of those so-called “Pie-Chart antennas”: an extension of the mutual inductance compensation method to higher number of channels using symmetries. We detail the simple iterative building process of those antennas, illustrate it with numerical analysis and evaluate there effectiveness via real experiments on the 3-channels PCB array and the 2-channels rotary array up to the limit of our test setup. The Pie Chart design is primarily intended as an alternative solution to costly electronic filters or cumbersome EM shields in wireless AND wired applications, but not exclusively.
This work presents a spiral antenna array, which can be used in the V- and W-Band. An array equipped with Dolph-Chebychev coefficients is investigated to address issues related to the low gain and side lobe level of the radiating structure. The challenges encountered in this achievement are to provide an antenna that is not only good matched but also presents an appreciable effective bandwidth at the frequency bands of interest. Its radiation properties including the effective bandwidth and the gain are analyzed for the W-Band.
Integrated power semiconductors are often used for applications with cyclic on-chip power dissipation. This leads to repetitive self-heating and thermo-mechanical stress, causing fatigue on the on-chip metallization and possibly destruction by short circuits. Because of this, an accurate simulation of the thermo-mechanical stress is needed already during the design phase to ensure that lifetime requirements are met. However, a detailed thermo mechanical simulation of the device, including the on-chip metallization is prohibitively time-consuming due to its complex structure, typically consisting of many thin metal lines with thousands of vias. This paper introduces a two-step approach as a solution for this problem. First, a simplified but fast simulation is performed to identify the device parts with the highest stress. After, precise simulations are carried out only for them. The applicability of this method is verified experimentally for LDMOS transistors with different metal configurations. The measured lifetimes and failure locations correlate well with the simulations. Moreover, a strong influence of the layout of the on-chip metallization lifetime was observed. This could also be explained with the simulation
method.
This paper investigates the electrothermal stability and the predominant defect mechanism of a Schottky gate AlGaN/GaN HEMT. Calibrated 3-D electrothermal simulations are performed using a simple semiempirical dc model, which is verified against high-temperature measurements up to 440°C. To determine the thermal limits of the safe operating area, measurements up to destruction are conducted at different operating points. The predominant failure mechanism is identified to be hot-spot formation and subsequent thermal runaway, induced by large drain–gate leakage currents that occur at high temperatures. The simulation results and the high temperature measurements confirm the observed failure patterns.
We present a fully automatic approach to real-time 3D face reconstruction from monocular in-the-wild videos. With the use of a cascaded-regressor-based face tracking and a 3D morphable face model shape fitting, we obtain a semidense 3D face shape. We further use the texture information from multiple frames to build a holistic 3D face representation from the video footage. Our system is able to capture facial expressions and does not require any person specific training. We demonstrate the robustness of our approach on the challenging 300 Videos in the Wild (300- VW) dataset. Our real-time fitting framework is available as an open-source library at http://4dface.org.
Nowadays CHP units are discussed for the production of electricity on demand rather than for generation of heat providing electricity as a by-product. By this means, CHP units are capable of satisfying a higher share of the electricity demand on-site and in this new role, CHP units are able to reduce the load on the power grid and to compensate for high fluctuations of solar and wind power.
Evidently, a novel control strategy for CHP units is required in order to shift the operation oriented at the heat demand to an operation led by the electricity demand. Nevertheless, the heat generated by the CHP unit needs to be utilized completely in any case, for maintaining energy as well as economic efficiency. Such a strategy has been developed at Reutlingen University, and it will be presented in the paper. Part of the strategy is an intelligent management for the thermal energy storage (TES) ensuring that the storage is at low level in terms of its heat content just before an electricity demand is calling the CHP unit into operation. Moreover, a proper forecast of both, heat and electricity demand, is incorporated and the requirements of the CHP unit in terms of maintenance and lifetime are considered by limiting the number of starts and stops per unit time and by maintaining a certain minimum length of the operation intervals.
All aspects of this novel control strategy are revealed in the paper, which has been implemented on a controller for further testing at two sites in the field. Results from these tests are given as well as results from a simulation model, which is able to evaluate the performance of the control strategy for an entire year.
This article covers the design of highly integrated gate drivers and level shifters for high-speed, high power efficiency and dv/dt robustness with focus on automotive applications. With the introduction of the 48 V board net in addition to the conventional 12 V battery, there is an increasing need for fast switching integrated gate drivers in the voltage range of 50 V and above. State-of-the-art drivers are able to switch 50 V in less than 5 ns. The high-voltage electrical drive train demands for galvanic isolated and highly integrated gate drivers. A gate driver with bidirectional signal transmission with a 1 MBit/s amplitude modulation, 10/20 MHz frequency modulation and power transfer over one single transformer will be discussed. The concept of high-voltage charge storing enables an area-efficient fully integrated bootstrapping supply with 70 % less area consumption. EMC is a major concern in automotive. Gate drivers with slope control optimize EMC while maintaining good switching efficiency. A current mode gate driver, which can change its drive current within 10 ns, results in 20 dBuV lower emissions between 7 and 60 MHz and 52 % lower switching loss compared to a conventional constant current gate driver.