Refine
Document Type
- Conference proceeding (273)
- Journal article (153)
- Book chapter (23)
- Book (22)
- Patent / Standard / Guidelines (15)
- Report (9)
- Doctoral Thesis (7)
- Working Paper (5)
- Anthology (2)
Is part of the Bibliography
- yes (509)
Institute
- Technik (509) (remove)
Publisher
- IEEE (141)
- VDE Verlag (42)
- Springer (34)
- Elsevier (25)
- Hochschule Ulm (12)
- Public Verlagsgesellschaft und Anzeigenagentur (11)
- Hochschule Reutlingen (9)
- Association for Computing Machinery (8)
- Hanser (7)
- MDPI (7)
An interactive clothing design and a personalized virtual display with user’s own face are presented in this paper to meet the requirement of personalized clothing customization. A customer interactive clothing design approach based on genetic engineering ideas is analyzed by taking suit as an example. Thus, customers could rearrange the clothing style elements, chose available color, fabric and come up with their own personalized suit style. A web 3D customization prototype system of personalized clothing is developed based on the Unity3D and VR technology. The layout of the structure and functions combined with the flow of the system are given. Practical issues such as 3D face scanning, suit style design, fabric selection, and accessory choices are addressed also. Tests to the prototype system indicate that it could show realistic clothing and fabric effect and offer effective visual and customization experience to users.
Usually battery chargers have two stages and DC charging current is considered to by necessary for a proper charging. To decrease the charger volume, a single stage LLC battery charger is investigated in this paper. PFC stage is eliminated, therefore no bulky capacitor is necessary any more, and battery is charged with a sinusoidal-like charging current. However, previous studies show that such a pulsating charging current has only minimal impact on battery life and efficiency. Design considerations of the resonant tank and optimal transformer design are presented. A 360W single stage LLC converter prototype for e-bike charger achieves a power factor of 0.98, efficiency of 0.93 and power density of 1,8kW/dm³.
This paper presents a permanent magnet tubular linear generator system for powering passive sensors using vertical vibration harvesting energy. The system consists of a permanent magnet tubular linear vibration generator and electric circuits. By using the design of mechanical resonant movers, the generator is capable of converting low frequencies small amplitude vertical vibration energy into more regular sinusoidal electrical energy. The distribution of the magnetic field and electromotive force are calculated by Finite Element Analysis. The characteristics of the linear vibration generator system are observed. The experimental results show the generator can produce about 0.4W~1.6W electrical power when the vibration source's amplitude is fixed on 2mm and the frequencies are between 13Hz and 22Hz.
DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.
DMOS transistors often suffer from substantial self-heating during high power dissipation, which can lead to thermal destruction if the device temperature reaches excessive values. A successfully demonstrated method to reduce the peak temperature is the redistribution of power dissipation density from the hotter to the cooler device areas by careful layout modification. However, this is very tedious and time-consuming if complex-shaped devices as often found in industrial applications are considered.
This paper presents an approach for fully automatic layout optimization which requires only a few hours processing time. The approach is applied to complex shaped test structures which are investigated by measurements and electro-thermal simulations. Results show a significantly lower peak temperature and an energy capability gain of 84 %, offering potential for a 18 % size reduction of active area.
In dieser Arbeit wird eine optimierte Bandgap-Referenz zur Erzeugung einer temperaturstabilen Spannung und eines Referenzstroms vorgestellt. Für Low-Power-Anwendungen wurde die Bandgap-Referenz, basierend auf der Brokaw-Zelle, mit minimaler Stromaufnahme und optimierter Chipfläche durch Multi-Emitter-Layout der Bipolartransistoren implementiert. Zusätzliches Merkmal ist ein verbreiteter Versorgungsspannungsbereich von 2,5 bis 5,5 V. Simulationen zeigen, dass eine stabile Ausgangsspannung von 1,218 V und ein Referenzstrom von 1,997 μA realisiert wird. Im Temperaturbereich -40 °C … 50 °C sowie dem gesamten Bereich der Versorgungsspannung beträgt die Genauigkeit der Referenzspannung ± 0,04 % mit einer Gesamtstromaufnahme zwischen 3,5 und 10 μA. Es wird eine Temperaturdrift von 2,18 ppm/K erreicht. Durch das elektronische Trimmen von Widerständen wird der Offset der Ausgangsspannung, bedingt durch Herstellungstoleranzen, auf ±3,5 mV justiert. Die Referenz wird in einer 0,18 μm BiCMOS-Technologie implementiert.
In this paper, it aims to model wind speed time series at multiple sites. The five-parameter Johnson distribution is deployed to relate the wind speed at each site to a Gaussian time series, and the resultant m-dimensional Gaussian stochastic vector process Z(t) is employed to model the temporal-spatial correlation of wind speeds at m different sites. In general, it is computationally tedious to obtain the autocorrelation functions (ACFs) and cross-correlation functions (CCFs) of Z(t), which are different to those of wind speed times series. In order to circumvent this correlation distortion problem, the rank ACF and rank CCF are introduced to characterize the temporal-spatial correlation of wind speeds, whereby the ACFs and CCFs of Z(t) can be analytically obtained. Then, Fourier transformation is implemented to establish the cross-spectral density matrix of Z(t), and an analytical approach is proposed to generate samples of wind speeds at m different sites. Finally, simulation experiments are performed to check the proposed methods, and the results verify that the five-parameter Johnson distribution can accurately match distribution functions of wind speeds, and the spectral representation method can well reproduce the temporal-spatial correlation of wind speeds.
Lehr- und Übungsbuch sowie Nachschlagewerk zur CAD-Software Creo Parametric und zu den Grundlagen der Produktdatenverwaltung mit Windchill. Vermittelt werden die Volumenmodellierung, die 3D Flächenmodellierung, die Blechmodellierung, die Baugruppen- und Zeichnungserstellung, das Erstellen von Animationen, die Definition und Anwendung kinematischer sowie dynamischer Analysen und die Definition von Baugruppen, die Konstruktionsvarianten "Top-Down" und "Bottom-Up" sowie die Organisation von Konstruktionsprojekten über Skelett Techniken.
Weiter werden die Grundlagen des Produktdatenmanagements im Konstruktionsbereich unter Windchill vermittelt. Alle Verfahren werden handlungsorientiert an einem weitgehend durchgehenden Modellierungsprojekt erarbeitet. Aufgrund des ausführlichen Inhalts- und Sachwortverzeichnisses sowie einer Vielzahl an Bildern ist das Buch als Grundlage für Vorlesungen, Schulungen oder Praktika und insbesondere auch zum Selbststudium sowie als Nachschlagewerk geeignet.
Lehrbuch zur CAD-Software Creo Parametric und zur Produktdatenverwaltung mit Windchill.
3D-Volumenmodellierung, 3D-Flächenmodellierung, Blechmodellierung, Baugruppen- und Zeichnungserstellung, Definition von Normteilen, Erstellen von Animationen und dynamischen Analysen.
Verfahren zum Umgang mit großen Baugruppen und zur flexiblen Modellierung, Konstruk-tionsvarianten "Top-Down" und "Bottom-Up", Organisation von Konstruktionsprojekten über Skeletttechnik.
Neu: Konstruktion von und mit Mehrkörperobjekten, Rahmenkonstruktion in der Profilumgebung (AFX), intelligente Verbindungen (IFX), Live Simulation und Generatives Design.
A millimeter-wave power amplifier concept in an advanced silicon germanium (SiGe) BiCMOS technology is presented. The goal of the concept is to investigate the impact of physical limitations of the used heterojunction bipolar transistors (HBT) on the performance of a 77 GHz power amplifier. High current behavior, collectorbase breakdown and transistor saturation can be forced with the presented design. The power amplifier is manufactured in an advanced SiGe BiCMOS technology at Infineon Technologies AG with a maximum transit frequency fT of around 250 GHz for npn HBT’s [1]. The simulation results of the power amplifier show a saturated output power of 16 dBm at a power added efficiency of 13%. The test chip is designed for a supply voltage of 3.3 V and requires a chip size of 1.448 x 0.930 mm².
Aimed at the problem that the accuracy of face image classification in complex environment is not high, a network model F-Net suitable for aesthetic classification of face images is proposed. Based on LeNet-5, the model uses convolutional layers to extract facial image features in complex backgrounds, optimized parameters in the network model, and changes the number of convolutional layers and fully connected layer feature elements in the model. The experimental results show that the F-Net network model proposed in this paper has a face image classifation accuracy of 73% in complex environment background, which is better than other classical convolutional neural network classification models.
We propose a novel technique to compensate the effects of R-C / gm-C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with tunable circuit structures, such as current-steering digital-to-analog converters (DAC). This approach constitutes an alternative or supplement to existing compensation techniques, including capacitor or gm tuning. We apply the proposed technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure. A feedback path tuning scheme is derived analytically and confirmed numerically using behavioral simulations. The modulator circuit was implemented in a 0.35-μm CMOS process using an active feedback coefficient tuning structure based on current-steering DACs. Post-layout simulations show that with this tuning structure, constant performance and stable operation can be obtained over a wide range of TC variation.
Verification of an active time constant tuning technique for continuous-time delta-sigma modulators
(2022)
In this work we present a technique to compensate the effects of R-C / g m -C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with finely tunable circuit structures, such as current-steering digital-to-analog converters (DAC). We apply our technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure, implemented in a 0.35-μm CMOS process. A tuning scheme for the reference currents of the feedback DACs is derived as a function of the individual TC errors and verified by circuit simulations. We confirm the tuning technique experimentally on the fabricated circuit over a TC parameter variation range of ±20%. Stable modulator operation is achieved for all parameter sets. The measured performances satisfy the expectations from our theoretical calculations and circuit-level simulations.
We present the results of an extensive characterization of the performance and stability of a third-order continuous-time delta-sigma modulator with active coefficient error compensation. Using our previously published coefficient tuning technique, process variation induced R-C time-constant (TC) errors in the forward signal path can be compensated indirectly using continuously tunable DACs in the feedback path. To validate our technique experimentally with a range of real TC variations, we designed a modulator with discretely configurable integration capacitor arrays in a 0.35-μm CMOS process. We configured the capacitors of the fabricated device for a range of total TC variations from -28.4 % to +19.3 % and measured the signal-to-noise ratio (SNR) as a function of the input amplitude before and after compensating the variations electrically using the feedback DACs. The results show that our tuning technique is capable of restoring the desired nominal modulator performance over the entire parameter variation range, including the system’s nominal maximum stable amplitude (MSA).
Um die ökologischen und ökonomischen Potenzaile der Elektromobilität zu nutzen, setzen kommunale Energieversorger heute auf das Betreiben öffentlicher Ladestationen, den Handel mit Ladestationen und das Bereitstellen spezieller Elektromobilitätstarife; ebenso auf elektrifiziertes Carsharing oder das Vermieten elektrifizierter Fahrzeuge und den Betrieb elektrifizierter Omnibusse im ÖPNV. Auch die Entwicklung und Planung individueller Elektromobilitätskonzepte, teils in Kombination mit Photovoltaikanlage, gehören in einigen Unternehmen zum Portfolio. Für die Zukunft sollten Stadtwerke ihre Aktivitäten im Bereich Elektromobilität an individuell definierten Zielen und Strategien ausrichten.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum conversion ratio are limited by the duty cycle of a PWM signal. In DCDC converters, a sawtooth generator is the fundamental circuit block to generate the PWM signal. The presented PWM generator is based on two parallel, fully interleaved PWM generator stages, each containing an integrator based sawtooth generator and two 3-stage highspeed comparators. A digital multiplexing of the PWM signals of each stage eliminates the dependency of the minimum on-time on the large reset times of the sawtooth ramps. A separation of the references of the PWM comparators in both stage allows to configure the PWM generator for a DCDC converter operating in fixed frequency or in constant on-time mode, which requires an operation in a wide frequency range. The PWM generator was fabricated in an 180 nm HV BiCMOS technology, as part of a DCDC converter. Measurements confirm minimum possible ontime pulses as short as 2 ns and thus allows switching frequencies of DCDC converters of >50 MHz at small duty cycle of <10%. At moderate duty cycles switching frequencies up to 100 MHz are possible.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. This leads especially at a high input voltage to a decreasing efficiency caused by switching losses. Conventional calculations are not suitable to predict the efficiency as parasitic capacitances have a significant loss contribution. This paper presents an analytical efficiency model which considers parasitic capacitances separately and calculates the power loss contribution of each capacitance to any resistive element. The proposed model is utilized for efficiency optimization of converters with switching frequencies >10MHz and input voltages up to 40V. For experimental evaluation a DCDC converter was manufactured in a 180 nm HV BiCMOS technology. The model matches a transistor level simulation and measurement results with an accuracy better than 3.5 %. The accuracy of the parasitic capacitances of the high voltage transistor determines the overall accuracy of the efficiency model. Experimental capacitor measurements can be fed into the model. Based on the model, different architectures have been studied.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.