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Electronic design automation approaches can roughly be divided into optimizers and procedures. While the former have enabled highly automated synthesis flows for digital integrated circuits, the latter play a vital (but mostly underestimated role) in the analog domain. This paper describes both automation strategies in comparison, identifying two fundamentally different automation paradigms that reflect the two basic design practices known as “top-down” and “bottom-up”. Then, with a focus on the latter, the history of procedural approaches is traced from their
early beginnings until today’s evolvements and future prospects to underline their practical importance and to accentuate their scientific value, both in itself and in the overall context of EDA.
While digital IC design is highly automated, analog circuits are still handcrafted in a time-consuming, manual fashion today. This paper introduces a novel Parameterized Circuit Description Scheme (PCDS) for the development of procedural analog schematic generators as parameterized circuits. Circuit designers themselves can use PCDS to create circuit automatisms which capture valuable expert knowledge, offer full topological flexibility, and enhance the re-use of well-established topologies. The generic PCDS concept has been successfully implemented and employed to create parameterized circuits for a broad range of use cases. The achieved results demonstrate the efficiency of our PCDS approach and the potential of parameterized circuits to increase automation in circuit design, also to benefit physical design by promoting the common schematic-driven-layout flow, and to enhance the applicability of circuit synthesis approaches.
IC layout automation with self-organized wiring and arrangement of responsive modules (SWARM)
(2019)
Focused on automating analog IC layout, the multi-agent-system Self-organized Wir ing and Arrangement of Responsive Modules (SWARM) combines the powers of pro-cedural generators and algorithmic optimization into a novel bottom-up meets top-down flow of supervised layout module interaction. Provoking self-organization via the effect of emergence, examples show SWARM finding even optimal placement solutions and producing constraint-compliant layout blocks which fit into a specified zone.
The limited interfaces of today's IC design environments for editing PCell parameters hinder a solid advancement towards more complex analog PCell modules. This paper presents Hierarchical Instance Parameter Editing (HIPE), a highly flexible concept for the customization of PCell sub-instances. Introducing a new type of parameter, HIPE facilitates the dynamic creation of multi-level editing forms reflecting the actual contents of a PCell instance. This approach greatly improves a PCell's ease-of-use, substantially simplifies PCell development, and allows for a hierarchical execution of parameter validation callbacks. Our HIPE implementation has been integrated into a professional PCell development tool and represents a key enabling technology for upcoming generations of high-level hierarchical PCells.
Optimization-based design automation for analog ICs still remains behind the demands. A promising alternative is given by procedural approaches such as parameterized generators, also known as PCells. We are working on a complete analog design flow based on parameterized generators for entire circuits and corresponding layout modules. Because the conventional programming of such enhanced generators is far too complicated and costly, new methods are needed to ease their development. This paper presents gPCDS (graphical PCDS), a novel tool for a designer-oriented development of schematic module generators, integrated into a common schematic entry environment. The tool is based on PCDS (Parameterized Circuit Description Scheme), a meta-language for the creation of parametrized analog circuits. Schematic module generators are a very desirable complement to layout module generators in order to achieve a seamless schematic- driven layout design flow on module level. By facilitating a way of generator development that matches a design expert’s mentality, gPCDS contributes to close this gap in the analog design flow.
In practice, the use of layout PCells for analog IC design has not advanced beyond primitive devices and simple modules. This paper introduces a Constraint-Administered PCell-Applying Blocklevel Layout Engine (CAPABLE) which permits PCells to access their context, thus enabling a true "bottom-up" development of complex parameterized modules. These modules are integrated into the design flow with design constraints and applied by an execution cockpit via an automatically built layout script. The practical purpose of CAPABLE is to easily generate full-custom block layouts for given schematic circuits. Perspectively, our results inspire a whole new conception of PCells that can not only act (on demand), but also react (to environmental changes) and interact (with each other).
This paper enhances SWARM, a novel deterministic analog layout automation approach based on the idea of cellular automata. SWARM implements a decentralized interaction model in which responsive layout modules, covering basic circuit types, autonomously move, rotate and deform themselves to let constraint-compliant, compact layout solutions emerge from a synergetic flow of self-organization. With the ability to consider design constraints both implicitly and explicitly, SWARM joins the layout quality of procedural generators with the flexibility of optimization algorithms, combining these two kinds of automation into a “bottom-up meets top-down” flow. The new enhancements are demonstrated in an OTA example, depicting the power of SWARM and its enormous potential for future developments.
In analog layout design, chip floorplans are usually still handcrafted by human experts. Particularly, the nondiscrete variability of block dimensions must be exploited thereby, which is a serious challenge for optimization-based algorithmic floorplanners. This paper presents a fundamentally new automation approach based on self-organization, in which floorplan blocks can autonomously move, rotate and deform themselves to jointly let compact results emerge from a synergistic flow of interaction. Our approach is able to minimize area and wirelength, supports nonslicing floorplan structures, can consider fully variable block dimensions, accounts for a fixed rectilinear boundary, and works absolutely deterministic. The approach is innovatively different from conventional, top-down oriented floorplanning algorithms.