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Boost converters suffer from a bandwidth limitation caused by the right-half plane zero (RHPZ), which occurs in the control-to-output transfer function. In contrast, there are many applications that require superior dynamic behavior. Further, size and cost of boost converter systems can be minimized by reduced voltage deviations and fast transient responses in case of large signal load transients. The key idea of the proposed ΔV/Δt-intervention control concept is to adapt the controller output to its new steady state value immediately after a load transient by prediction from known parameters. The concept is implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology and a Xilinx Spartan-6 field programmable gate array (FPGA). In a boost converter with 3.5V input voltage, 6.3V output voltage, 1.2A load, and 500 kHz switching frequency, the output voltage deviations are 2.8x smaller, scaling down the output capacitor value by the same factor. The recovery times are 2.4x shorter in case of large signal load transients with the proposed concept. The control is widely applicable, as it supports constant switching frequencies and allows for duty cycle and inductor current limitations. It also shows various advantages compared to conventional control and to selected adaptive control concepts.
In recent years, significant progress was made on switched-capacitor DCDC converters as they enable fully integrated on chip power management. New converter topologies overcame the fixed input-to-output voltage limitation and achieved high efficiency at high power densities. SC converters are attractive to not only mobile handheld devices with small input and output voltages, but also for power conversion in IoTs, industrial and automotive applications, etc. Such applications need to be capable of handling high input voltages of more than 10V. This talk highlights the challenges of the required supporting circuits and high voltage techniques, which arise for high Vin SC converters. It includes level shifters, charge pumps and back-to-back switches. High Vin conversion is demonstrated in a 4:1 SC DCDC converter with an input voltage as high as 17V with a peak efficiency of 45 %, and a buckboost SC converter with an input voltage range starting from 2 up to 13V, which utilizes a total of 17 ratios and achieves a peak efficiency of 81.5 %. Furthermore a highly integrated micro power supply approach is introduced, which is connected directly to the 120/230 Vrms mains, with an output power of 3mW, resulting in a power density >390μW/mm², which exceeds prior art by a factor of 11.
Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
In a digitally controlled slope shaping system, reliable detection of both voltage and current slope is required to enable a closed-loop control for various power switches independent of system parameters. In most state-of-the-art works, this is realized by monitoring the absolute voltage and current values. Better accuracy at lower DC power loss is achieved by sensing techniques for a reliable passive detection, which is achieved through avoiding DC paths from the high voltage network into the sensing network. Using a high-speed analog-to-digital converter, the whole waveform of the transient derivative can be stored digitally and prepared for a predictive cycle-by-cycle regulation, without requiring high-precision digital differentiation algorithms. To gain an accurate representation of the voltage and current derivative waveforms, system parasitics are investigated and classified in three sections: (1) component parasitics, which are identified by s-parameter measurements and extraction of equivalent circuit models, (2) PCB design issues related to the sensing circuit, and (3) interconnections between adjacent boards.
The contribution of this paper is an optimized sensing network on the basis of the experimental study supporting fast transition slopes up to 100 V/ns and 1 A/ns and beyond, making the sensing technique attractive for slope shaping of fast switching devices like modern generation IGBTs, CoolMOSTM and SiC mosfets. Measurements of the optimized dv/dt and di/dt setups are demonstrated for a hard switched IGBT power stage.
Galvanic isolated gate drivers require a control signal as well as energy transmission from the control side (lowside) to the driver side (high-side). An additional backward signal transmission is preferred for error signals, status information, etc. This is often realized by means of several transformers or opto-couplers. Decreasing the number of isolation elements results in lower cost and a higher degree of miniaturization. This work presents a gate driver with bidirectional signal transmission and energy transfer via one single transformer. The key concept proposed in this paper is to combine bootstrapping to deliver the main gate charge for the driven power switch with additional energy transfer via the signal transformer. This paper also presents a very efficient combination of energy transfer to two high-side supply rails with back channel amplitude modulation. This way an isolated gate driver can be implemented that allows 100% pulse-width modulation (PWM) duty cycle at low complexity and system cost. The proposed high-side driver IC with integrated power supply, modulation and demodulation circuits was manufactured in a 180nm high-voltage BiCMOS technology. Measurements confirm the concept of bidirectional signal transmission with a 1MBit/s amplitude modulation, 10/20MHz frequency modulation and a maximum power transmission of 14mW via the transformer.
This paper presents a fully integrated gate driver in a 180-nm bipolar CMOS DMOS (BCD) technology with 1.5-A max. gate current, suitable for normally OFF gallium nitride (GaN) power switches, including gate-injection transistors (GIT). Full-bridge driver architecture provides a bipolar and three-level gate drive voltage for a robust and efficient GaN switching. The concept of high voltage energy storing (HVES), which comprises an on-chip resonant LC tank, enables a very area-efficient buffer capacitor integration and superior gatedriving speed. It reduces the component count and the influence of parasitic gate-loop inductance. Theory and calculations confirm the benefits of HVES compared to other capacitor implementation methods. The proposed gate driver delivers a gate charge of up to 11.6 nC, sufficient to drive most types of currently available GaN power transistors. Consequently, HVES enables to utilize the fast switching capabilities of GaN for advanced and compact power electronics.
This article covers the design of highly integrated gate drivers and level shifters for high-speed, high power efficiency and dv/dt robustness with focus on automotive applications. With the introduction of the 48 V board net in addition to the conventional 12 V battery, there is an increasing need for fast switching integrated gate drivers in the voltage range of 50 V and above. State-of-the-art drivers are able to switch 50 V in less than 5 ns. The high-voltage electrical drive train demands for galvanic isolated and highly integrated gate drivers. A gate driver with bidirectional signal transmission with a 1 MBit/s amplitude modulation, 10/20 MHz frequency modulation and power transfer over one single transformer will be discussed. The concept of high-voltage charge storing enables an area-efficient fully integrated bootstrapping supply with 70 % less area consumption. EMC is a major concern in automotive. Gate drivers with slope control optimize EMC while maintaining good switching efficiency. A current mode gate driver, which can change its drive current within 10 ns, results in 20 dBuV lower emissions between 7 and 60 MHz and 52 % lower switching loss compared to a conventional constant current gate driver.
The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm². The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm². This exceeds prior art by a factor of 11.
There is a growing need for motor drives with improved EMC in various automotive and industrial applications. An often referenced approach to reduce EME is to change the shape of the switching signal to reduce the EMI caused by the voltage and current transitions. This requires very precise gate control of the power MOSFET to achive better switching behaviour and lower EME without a major increase in switching losses. In order to find an optimal trade-off, this work utilizes a monolithic current mode gate driver with a variable output current that can be changed within 10ns. With this driver, measurements with different gate current profiles were taken. The di/dt transition was confirmed to be as important as the dv/dt transition in the power MOSFET. As a result of the improved switching behavior the emissions were reduced by up to 20dB between 7MHz and 60MHz with a switching loss that is 52% lower than with a constantly low gate current.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. This leads especially at a high input voltage to a decreasing efficiency caused by switching losses. Conventional calculations are not suitable to predict the efficiency as parasitic capacitances have a significant loss contribution. This paper presents an analytical efficiency model which considers parasitic capacitances separately and calculates the power loss contribution of each capacitance to any resistive element. The proposed model is utilized for efficiency optimization of converters with switching frequencies >10MHz and input voltages up to 40V. For experimental evaluation a DCDC converter was manufactured in a 180 nm HV BiCMOS technology. The model matches a transistor level simulation and measurement results with an accuracy better than 3.5 %. The accuracy of the parasitic capacitances of the high voltage transistor determines the overall accuracy of the efficiency model. Experimental capacitor measurements can be fed into the model. Based on the model, different architectures have been studied.
The efficiency impact of air-cored inductors used close to and beyond its cut-off frequency in multi-MHz converters is investigated. A method is presented to determine the converter switching frequency that causes the lowest losses in a given inductor. Influential parameters are analysed to optimize an inductor for a predefined switching frequency.
A concept for a slope shaping gate driver IC is proposed, used to establish control over the slew rates of current and voltage during the turn-on and turn off switching transients.
It combines the high speed and linearity of a fully-integrated closed-loop analog gate driver, which is able to perform real-time regulation, with the advantages of digital control, like flexibility and parameter independency, operating in a predictive cycle-bycycle regulation. In this work, the analog gate drive integrated circuit is partitioned into functional blocks and modeled in the small-signal domain, which also includes the non-linearity of parameters. An analytical stability analysis has been performed in order to ensure full functionality of the system controlling a modern generation IGBT and a superjunction MOSFET. Major parameters of influence, such as gate resistor and summing node capacitance, are investigated to achieve stable control. The large-signal behavior, investigated by simulations of a transistor level design, verifies the correct operation of the circuit. Hence, the gate driver can be designed for robust operation.
Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time.
Digital control design bears challenges like the prevention of limit cycle oscillations and controller wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digitalconverter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital converters in digitally controlled SMPS.
Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 μs-latency of a 16-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies.
Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.
The increasing slew rate of modern power switches can increase the efficiency and reduce the size of power electronic applications. This requires a fast and robust signal transmission to the gate driver of the high-side switch. This work proposes a galvanically isolated capacitive signal transmission circuit to increase common mode transient immunity (CMTI). An additional signal path is introduced to significantly improve the transmission robustness for small duty cycles to assure a safe turn-off of the power switch. To limit the input voltage range at the comparator on the secondary side during fast high-side transitions, a clamping structure is implemented. A comparison between a conventional and the proposed signal transmission is performed using transistor level simulations. A propagation delay of about 2 ns over a wide range of voltage transients of up to 300V/ns at input voltages up to 600V is achieved.
Bootstrap circuits are mainly used for supplying a gate driver circuit to provide the gate overdrive voltage for a high-side NMOS transistor. The required charge has to be provided by a bootstrap capacitor which is often too large for integration if an acceptable voltage dip at the capacitor has to be guaranteed. Three options of an area efficient bootstrap circuit for a high side driver with an output stage of two NMOS transistors are proposed. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and connected when the gate driver turns on. A high voltage swing at the second capacitor leads to a high charge allocation. Both bootstrap capacitors require up to 70% less area compared to a conventional bootstrap circuit. This enables compact power management systems with fewer discrete components and smaller die size. A calculation guideline for optimum bootstrap capacitor sizing is given. The circuit was manufactured in a 180nm high-voltage BiCMOS technology as part of a high-voltage gate driver. Measurements confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit including two stacked 75.8pF and 18.9pF capacitors results in a voltage dip lower than 1V. This matches well with the theory of the calculation guideline.
Size and cost of a boost converter can be minimized by reducing the voltage overshoot and fastening the transient response in case of load transient. The presented technique improves the transient response of a current mode controlled boost converter, which usually suffers from bandwidth limitation because of its right-half-plane zero (RHPZ). The proposed technique comprises a load current estimation which works as part of a digital controller without any additional measurements. Based on the latest load estimation the controller parameters are adapted, achieving small voltage overshoot and fast transient response. The presented technique was implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology, a Xilinx Spartan-6 field programmable gate array (FPGA), and a TI-ADS8422 analog to-digital-converter (ADC). Simulation and measurements of a 4V-to-6.3V, 500mA boost converter show an improvement of 50% in voltage overshoot and response time to load transient.
For area reasons, NMOS transistors are preferred over PMOS for the pull-up path in gate drivers. Bootstrapping has to ensure sufficient NMOS gate overdrive. Especially in high-current gate drivers with large transistors, the bootstrap capacitor is too large for integration. This paper proposes three options of fully integrated bootstrap circuits. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and ensures high charge allocation when the driver turns on. A capacitor sizing guideline and the overall driver implementation including a suitable charge pump for permanent driver activation is provided. A linear regulator is used for bootstrap supply and it also compensates the voltage drop of the bootstrap diode. Measurements from a testchip in 180 nm high-voltage BiCMOS confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit with two stacked 75.8 pF and 18.9 pF capacitors results in an expected voltage dip of lower than 1 V. Both bootstrap capacitors require 70% less area compared to a conventional bootstrap circuit. Besides drivers, the proposed bootstrap can also be directly applied to power stages to achieve fully integrated switched mode power supplies or class-D output stages.
The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the presented integrated micropower supply. Connected to the 120/230-VRMS mains, it provides a 3.3-V ac output voltage, suitable for applications such as the Internet-of Things and smart homes. The micropower supply consists of a fully integrated ac–dc and dc–dc converter with one external low-voltage surface mount device buffer capacitor, resulting in an extremely compact size. Fabricated in a low-cost 0.35-μm 700-V complimentary metal-oxide-semiconductor technology, it covers a die size of 7.7 mm². The ac–dc converter is a direct coupled, full-wave rectifier with a subsequent series regulator. The dc–dc stage is a fully integrated capacitive 4:1 converter with up to 17-V input and 47.4% peak efficiency. The power supply comprises several high-voltage control circuits including level shifters and various types of charge pumps (CPs). A source supplied CP is utilized that supports a varying switching node potential. The overall losses are discussed and optimized, including flying capacitor bottom-plate losses. The power supply achieves an output power of 3 mW, resulting in a power density of 390 μW/mm². This exceeds prior art by a factor of 11.
A highly integrated synchronous buck converter with a predictive dead time control for input voltages >18 V with 10 MHz switching frequency is presented. A high resolution dead time of ˜125 ps allows to reduce dead time dependent losses without requiring body diode conduction to evaluate the dead time. High resolution is achieved by frequency compensated sampling of the switching node and by an 8 bit differential delay chain. Dead time parameters are derived in a comprehensive study of dead time depended losses. This way, the efficiency of fast switching DC-DC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching. High-speed circuit blocks for fast switching operation are presented including level shifter, gate driver, PWM generator. The converter has been implemented in a 180 nm high-voltage BiCMOS technology.
Multilevel-cell (MLC) flash is commonly deployed in today’s high density NAND memories, but low latency and high reliability requirements make it barely used in automotive embedded flash applications. This paper presents a time domain voltage sensing scheme that applies a dynamic voltage ramp at the cells’ control gate (CG) in order to achieve fast and reliable sensing suitable for automotive applications.
A millimeter-wave power amplifier concept in an advanced silicon germanium (SiGe) BiCMOS technology is presented. The goal of the concept is to investigate the impact of physical limitations of the used heterojunction bipolar transistors (HBT) on the performance of a 77 GHz power amplifier. High current behavior, collectorbase breakdown and transistor saturation can be forced with the presented design. The power amplifier is manufactured in an advanced SiGe BiCMOS technology at Infineon Technologies AG with a maximum transit frequency fT of around 250 GHz for npn HBT’s [1]. The simulation results of the power amplifier show a saturated output power of 16 dBm at a power added efficiency of 13%. The test chip is designed for a supply voltage of 3.3 V and requires a chip size of 1.448 x 0.930 mm².
This paper presents a dc–dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc–dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130 nm CMOS technology with an area of only 0.14 mm². It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.
This work presents a fully integrated GaN gate driver in a 180nm HV BCD technology that utilizes high-voltage energy storing (HVES) in an on-chip resonant LC tank, without the need of any external capacitor. It delivers up to 11nC gate charge at a 5V GaN gate, which exceeds prior art by a factor of 45-83, supporting a broad range of GaN transistor types. The stacked LC tank covers an area of only 1.44mm², which corresponds to a superior value of 7.6nC/mm².
Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ~1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.
A wide-bandwidth galvanically isolated current sensing circuit with an integrated Rogowski coil in 180nm CMOS is presented. Exploiting the high-frequency properties of an optimized on-chip Rogowski coil, currents can be measured up to a bandwidth of 75 MHz. The analog sensor front-end comprises a two-stage integrator, which allows a chopper frequency below signal bandwidth, resulting in 2.2 mVrms output noise. An additional integrated Hall sensor extends the measurement range towards DC.
A fast transient current-mode buckboost DC-DC converter for portable devices is presented. Running at 1 MHz the converter provides stable 3 V from a 2.7 V to 4.2 V Li-Ion battery. A small voltage under-/overshoot is achieved by fast transient techniques: (1) adaptive pulse skipping (APS) and (2) adaptive compensation capacitance (ACC). The proposed converter was implemented in a 0.25 μm CMOS technology. Load transient simulations confirm the effectiveness of APS and ACC. The improvement in voltage undershoot and response time at light-to-heavy load step (100 mA to 500 mA), are 17 % and 59 %, respectively, in boost mode and 40 % and 49 %, respectively, in buck mode. Similar results are achieved at heavy-to-light load step for overshoot and response time.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum conversion ratio are limited by the duty cycle of a PWM signal. In DCDC converters, a sawtooth generator is the fundamental circuit block to generate the PWM signal. The presented PWM generator is based on two parallel, fully interleaved PWM generator stages, each containing an integrator based sawtooth generator and two 3-stage highspeed comparators. A digital multiplexing of the PWM signals of each stage eliminates the dependency of the minimum on-time on the large reset times of the sawtooth ramps. A separation of the references of the PWM comparators in both stage allows to configure the PWM generator for a DCDC converter operating in fixed frequency or in constant on-time mode, which requires an operation in a wide frequency range. The PWM generator was fabricated in an 180 nm HV BiCMOS technology, as part of a DCDC converter. Measurements confirm minimum possible ontime pulses as short as 2 ns and thus allows switching frequencies of DCDC converters of >50 MHz at small duty cycle of <10%. At moderate duty cycles switching frequencies up to 100 MHz are possible.
This paper presents a digitally controlled boost converter IC for high output voltage and fast transient applications. Thus, it is well applicable in automotive and industrial environments. The 3V-to-6V input voltage, 6.3V output voltage, 1A boost converter IC is fabricated in a 180nm BCD technology. Digital control enables cost savings, advanced control concepts, and it is less parameter sensitive compared to common analog control. A 90 ns latency, 6-bit delay line ADC operates with a window concept, meeting high resolution requirements, e.g. in car battery applications. An output voltage live tracking is included for extending the ADC conversion window. A charge pump DAC provides high resolution, monotonicity, and short 128 ns conversion time. Further, a standard digital PI controller is enhanced by a simple but effective ΔV/Δt-intervention control. It results in 2.8x reduced output voltage deviations in case of load steps, scaling down the output capacitor value by the same factor.
The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high speed and power-efficient level shifter for voltages of up to 50V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv / dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40% compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180nm BiCMOS technology. Measurements confirm a 50V 120MHz high-speed operation of the level shifter with a rising / falling propagation delay of 1.45 ns / 1.3 ns, respectively. The dv / dt robustness has been confirmed by measurements for transitions up to 6V/ ns.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
This paper presents a wide-Vin step-down parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300-nH resonant coil, placed in parallel to a conventional buck converter. Soft-switching resonant converters are beneficial for high-Vin multi-MHz converters to reduce dominant switching losses, enabling higher switching frequencies. The output filter inductor is optimized based on an empirical study of available inductors. The study shows that faster switching significantly reduces not only the inductor value but also volume, price, and even the inductor losses. In addition, unlike conventional resonant concepts, soft-switching control as part of the proposed PRC eliminates input voltage-dependent losses over a wide operating range, resulting in 76.3% peak efficiency. At Vin = 48 V, a loss reduction of 35% is achieved compared with the conventional buck converter. Adjusting an integrated capacitor array, and selecting the number of oscillation periods, keeps the switching frequency within a narrow range. This ensures high efficiency across a wide range of Vin = 12–48 V, 100–500-mA load, and 5-V output at up to 25-MHz switching frequency. Thanks to the low output current ripple, the output capacitor can be as small
as 50 nF.
A high-voltage replica based current sensor is presented, along with challenges and design techniques which are rarely discussed in literature so far. The performance is evaluated by detailed small signal and large signal analysis. By dedicated placing of high-voltage cascode devices, while keeping as many low-voltage devices as possible, a high gain-bandwidth product is achieved. A decoupling and biasing circuit is introduced which improves the response time of the current sensor at on/off transitions by a factor of five. The current sensor is implemented in a 180nm HV BiCMOS technology. The sensor achieves a DC loop gain of 83 dB and a gain-bandwidth product of 7 MHz. With the proposed techniques, the gain-bandwidth product is increased by a factor of six. The measurable current range is between 60mA and 1.5 A. The performance is demonstrated in a 500 kHz buck converter at an input voltage of 40V. The overall circuit concept is suitable for 100V and beyond, enabling high performance power management designs including switched mode power supplies and motor applications.
DC-DC-converters are used in many different applications. Specifying the switching frequency is the most important parameter to calculate component costs and required space. Especially automotive applications of small brushed- or brushless dc-motors and the increasing number of DC-DC-converters have high requirements on the structual space (low box volume). This is of particular importance for automotive converters for the new 48 V board net. Multiplying the frequency by two will reduce the size of the power inductor by half at a given specification for output-voltage ripple. Smaller power inductors result in reduced losses due to smaller series resistance and parasitic capacitance. Furthermore a larger switching frequency decreases the size of the DC link capacitors. The circuit will get more idealized. However, as the switching losses increase with frequency, a DC-DC-converter can only benefit from these advantages if the switching behavior can be improved.
This paper presents an optimization method to increase switching slope and switching frequency of a 3.6 kW 3-phase step-up converter by separating the design and layout process into two parts. The first part is the power stage which carries the load current. It contains the power inductance and the drain-source-channel of the power MOSFETs. The second part is the driver circuit which contains the driver ICs, the gate resistor and the gate input impedance. While the switching slope was measured to be improved by 50 % , the switching time decreased by 20 %. Hence, the switching frequency of the step-up converter could be increased from 100 kHz to 200 kHz without loss increase. By mounting the driver ICs in a piggyback configuration in close proximity to the power stage, the parasitics could be further reduced significantly and 500 kHz switching frequency could be achieved with 97.5 % efficiency.
A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching
(2015)
Fast switching power supplies allow to reduce the size and cost of external passive components. However, the capacitive switching losses of the power stage will increase and become the dominant part of the total losses. Therefore, resonant topologies are the known key to reduce the losses of the power stage. A power switch with an additional resonant circuit can be turned on under soft-switching conditions, ideally with zero-voltage-switching (ZVS). As conventional resonant converts are only efficient for a constant load, this paper presents a predictive regulation loop to approach soft-switching conditions under varying load and component tolerances. A sample and hold based detection circuit is utilized to control the turn-on of the power switch by a digital regulation. The proposed design was fabricated in a 180 nm high-voltage BiCMOS technology. The efficiency of the converter was measured to be increased by up to 16 % vs. worst case timing and by 13 % compared to a conventional hard-switching buck converter at 20 V input voltage and at approximately 8 MHz switching frequency.
This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125 ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30%by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2A load. The peak efficiency is 81 %.
The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm². The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm². This exceeds prior art by a factor of 11.
The presented wide-Vin step-down converter introduces a parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300 nH resonant coil, placed in parallel to a conventional buck converter. Unlike conventional resonant concepts, the implemented soft-switching control eliminates input voltage dependent losses over a wide operating range. This ensures high efficiency across a wide range of Vin= 12-48V, 100-500mA load and 5V output at up to 15MHz switching frequency. The peak efficiency of the converter is 76.3 %. Thanks to the low output current ripple, the output capacitor can be as small as 50 nF, while the inductor tolerates a larger ESR, resulting in small component size. The proposed PRC architecture is also suitable for future power electronics applications using fast-switching GaN devices.
In recent years, significant progress has been made on switched-capacitor DC-DC converters as they enable fully integrated on-chip power management. New converter topologies overcame the fixed input-to-output voltage limitation and achieved high efficiency at high power densities. SC converters are attractive to not only mobile handheld devices with small input and output voltages, but also for power conversion in IoE, industrial and automotive applications, etc. Such applications need to be capable of handling widely varying input voltages of more than 10V, which requires a large amount of conversion ratios. The goal is to achieve a fine granularity with the least number of flying capacitors. In [1] an SC converter was introduced that achieves these goals at low input voltage VIN ≤ 2.5V. [2] shows good efficiency up to VIN = 8V while its conversion ratio is restricted to ≤1/2 with a limited, non-equidistant number of conversion steps. A particular challenge arises with increasing input voltage as several loss mechanisms like parasitic bottom-plate losses and gate-charge losses of high-voltage transistors become of significant influence. High input voltages require supporting circuits like level shifters, auxiliary supply rails etc., which allocate additional area and add losses [2-5]. The combination of both increasing voltage and conversion ratios (VCR) lowers the efficiency and the achievable output power of SC converters. [3] and [5] use external capacitors to enable higher output power, especially for higher VIN. However, this is contradictory to the goal of a fully integrated power supply.
An integrated synchronous buck converter with a high resolution dead time control for input voltages up to 48V and 10MHz switching frequency is presented. The benefit of an enhanced dead time control at light loads to enable zero voltage switching at both the high-side and low-side switch at low output load is studied. This way, compact multi-MHz DCDC converters can be implemented at high efficiency over a wide load current range. The concept also eliminates body diode forward conduction losses and minimizes reverse recovery losses. A dead time resolution of 125 ps is realized by an 8-bit differential delay chain. A further efficiency enhancement by soft switching at the high-side switch at light load is achieved with a voltage boost of the switching node by dead time control in forced continuous conduction mode. The monolithic converter is implemented in an 180nm high-voltage BiCMOS technology. At V IN = 48V, V OUT = 5V, 50mA load, 10MHz switching frequency and 500 nH output inductance, the efficiency is measured to be increased by 14.4% compared to a conventional predictive dead time control. A peak efficiency of 80.9% is achieved at 12V input.
More and more power electronics applications utilize GaN transistors as they enable higher switching frequencies in comparison to conventional Si devices. Faster switching shrinks down the size of passives and enables compact solutions in applications like renewable energy, electrical cars and home appliances. GaN transistors benefit from ~10× smaller gate charge QG and gate drive voltages in the range of typically 5V vs. ~15V for Si.
Modern power transistors are able to switch at very high transition speed, which can cause EMC violations and overshoot. This is addressed by a gate driver with variable gate current, which is able to control the transition speed. The key idea is that the gate driver can influence the di/dt and dv/dt transition separately and optimize whichever transition promises the highest improvement while keeping switching losses low. To account for changes in the load current, supply voltage, etc., a control loop is required in the driver to ensure optimized switching. In this paper, an efficient control scheme for an automotive gate driver with variable output current capability is presented. The effectiveness of the control loop is demonstrated for a MOSFET bridge consisting of OptiMOS-T2™devices with a total gate charge of 39nC. This bridge setup shows dv/dt transitions between 50 to 1000ns, depending on driving current. The driver is able to switch between gate current levels of 1 to 500mA in 10/15ns (rising/falling transition). With the implemented control loop the driver is measured to significantly reduce the ringing and thereby reduce device stress and electromagnetic emissions while keeping switching losses 52% lower than with a constant current driver.