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DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.
DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures, which can lead to device failure and reduced lifetime. Hence, it must be ensured that the device temperature does not rise too much. For this, the influence of the on-chip metallization must be taken into account because of the good thermal conductivity and significant thermal capacitance of the metal layers on top of the active DMOS area. In this paper, test structures with different metal layers and vias configurations are presented that can be used to determine the influence of the onchip metallization on the temperature caused by self-heating. It will be shown how accurate results can be obtained to determine even the influence of small changes in the metallization. The measurement results are discussed and explained, showing how on-chip metallization helps to lower the device temperature. This is further supported by numerical simulations. The obtained insights are valuable for technology optimization, but are also useful for calibration of temperature simulators.
The capability of the method of Immersion transmission ellipsometry (ITE) (Jung et al. Int Patent WO, 2004/109260) to not only determine three-dimensional refractive indices in anisotropic thin films (which was already possible in the past), but even their gradients along the z-direction (perpendicular to the film plane) is investigated in this paper. It is shown that the determination of orientation gradients in deep-sub-lm films becomes possible by applying ITE in combination with reflection ellipsometry. The technique is supplemented by atomic force microscopy for measuring the film thickness. For a photooriented thin film, no gradient was found, as expected. For a photo-oriented film, which was subsequently annealed in a nematic liquid crystalline phase, an order was found similar to the one applied in vertically aligned nematic displays, with a tilt angle varying along the z-direction. For fresh films, gradients were only detected for the refractive index perpendicular to the film plane, as expected.