Bootstrap circuits are mainly used for supplying a gate driver circuit to provide the gate overdrive voltage for a high-side NMOS transistor. The required charge has to be provided by a bootstrap capacitor which is often too large for integration if an acceptable voltage dip at the capacitor has to be guaranteed. Three options of an area efficient bootstrap circuit for a high side driver with an output stage of two NMOS transistors are proposed. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and connected when the gate driver turns on. A high voltage swing at the second capacitor leads to a high charge allocation. Both bootstrap capacitors require up to 70% less area compared to a conventional bootstrap circuit. This enables compact power management systems with fewer discrete components and smaller die size. A calculation guideline for optimum bootstrap capacitor sizing is given. The circuit was manufactured in a 180nm high-voltage BiCMOS technology as part of a high-voltage gate driver. Measurements confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit including two stacked 75.8pF and 18.9pF capacitors results in a voltage dip lower than 1V. This matches well with the theory of the calculation guideline.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. This leads especially at a high input voltage to a decreasing efficiency caused by switching losses. Conventional calculations are not suitable to predict the efficiency as parasitic capacitances have a significant loss contribution. This paper presents an analytical efficiency model which considers parasitic capacitances separately and calculates the power loss contribution of each capacitance to any resistive element. The proposed model is utilized for efficiency optimization of converters with switching frequencies >10MHz and input voltages up to 40V. For experimental evaluation a DCDC converter was manufactured in a 180 nm HV BiCMOS technology. The model matches a transistor level simulation and measurement results with an accuracy better than 3.5 %. The accuracy of the parasitic capacitances of the high voltage transistor determines the overall accuracy of the efficiency model. Experimental capacitor measurements can be fed into the model. Based on the model, different architectures have been studied.
For area reasons, NMOS transistors are preferred over PMOS for the pull-up path in gate drivers. Bootstrapping has to ensure sufficient NMOS gate overdrive. Especially in high-current gate drivers with large transistors, the bootstrap capacitor is too large for integration. This paper proposes three options of fully integrated bootstrap circuits. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and ensures high charge allocation when the driver turns on. A capacitor sizing guideline and the overall driver implementation including a suitable charge pump for permanent driver activation is provided. A linear regulator is used for bootstrap supply and it also compensates the voltage drop of the bootstrap diode. Measurements from a testchip in 180 nm high-voltage BiCMOS confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit with two stacked 75.8 pF and 18.9 pF capacitors results in an expected voltage dip of lower than 1 V. Both bootstrap capacitors require 70% less area compared to a conventional bootstrap circuit. Besides drivers, the proposed bootstrap can also be directly applied to power stages to achieve fully integrated switched mode power supplies or class-D output stages.
Galvanic isolated gate drivers require a control signal as well as energy transmission from the control side (lowside) to the driver side (high-side). An additional backward signal transmission is preferred for error signals, status information, etc. This is often realized by means of several transformers or opto-couplers. Decreasing the number of isolation elements results in lower cost and a higher degree of miniaturization. This work presents a gate driver with bidirectional signal transmission and energy transfer via one single transformer. The key concept proposed in this paper is to combine bootstrapping to deliver the main gate charge for the driven power switch with additional energy transfer via the signal transformer. This paper also presents a very efficient combination of energy transfer to two high-side supply rails with back channel amplitude modulation. This way an isolated gate driver can be implemented that allows 100% pulse-width modulation (PWM) duty cycle at low complexity and system cost. The proposed high-side driver IC with integrated power supply, modulation and demodulation circuits was manufactured in a 180nm high-voltage BiCMOS technology. Measurements confirm the concept of bidirectional signal transmission with a 1MBit/s amplitude modulation, 10/20MHz frequency modulation and a maximum power transmission of 14mW via the transformer.
Es wird ein hochintegrierter Gatetreiber für 600V-Anwendungen mit einer galvanischen Isolation zwischen der Ansteuerelektronik und der Treiberseite vorgestellt. Eine Besonderheit ist die bidirektionale Signalübertragung und die Energieversorgung über einen einzigen Transformator. Die Treiberansteuersignale werden mittels 10/20 MHz Frequenzmodulation übertragen. Die Signalrückübertragung ist in Form einer 1Mbit/s Amplitudenmodulation realisiert. Die Energieübertragung über den Transformator erlaubt ein dauerhaftes Einschalten des Treibers. Der Energiebedarf während des Schaltvorgangs wird hauptsächlich durch eine Bootstrapschaltung bereitgestellt. Eine weitere Besonderheit ist die Verwendung einer flächeneffizienten Integration einer NMOS Treiberausgangsstufe. Der Gatetreiber wurde in einer 180nm Hochvolt-BiCMOS-Technologie hergestellt. Messungen bestätigen die Funktion des Treibers.
Die vorliegende Erfindung betrifft eine Schaltungsanordnung mit einer Bootstrap-Schaltung, die zumindest eine Hauptkapazität aufweist, von der die erste Seite mit einem ersten Zweig der Schaltungsanordnung und die zweite Seite mit einem auf veränderlichem Potential liegenden zweiten Zweig der Schaltungsanordnung verbunden ist. Die vorgeschlagene Schaltungsanordnung zeichnet sich dadurch aus, dass die Bootstrap-Schaltung parallel zur Hauptkapazität wenigstens eine weitere Kapazität aufweist, die über eine zweite Versorgungsspannung auf eine höhere Spannung aufladbar ist als die Hauptkapazität und über wenigstens ein Schaltelement zur Unterstützung der Hauptkapazität zuschaltbar ist. Bei der vorgeschlagenen Schaltungsanordnung kann in Abhängigkeit von der Dimensionierung der Bootstrap-Kapazitäten eine sehr viel kleinere Fläche mit höherem oder gleich bleibenden Spannungseinbruch oder eine nicht so starke Flächenreduzierung mit kleinerem Spannungseinbruch verglichen mit einer herkömmlichen Bootstrap-Schaltung erzielt werden.
The increasing slew rate of modern power switches can increase the efficiency and reduce the size of power electronic applications. This requires a fast and robust signal transmission to the gate driver of the high-side switch. This work proposes a galvanically isolated capacitive signal transmission circuit to increase common mode transient immunity (CMTI). An additional signal path is introduced to significantly improve the transmission robustness for small duty cycles to assure a safe turn-off of the power switch. To limit the input voltage range at the comparator on the secondary side during fast high-side transitions, a clamping structure is implemented. A comparison between a conventional and the proposed signal transmission is performed using transistor level simulations. A propagation delay of about 2 ns over a wide range of voltage transients of up to 300V/ns at input voltages up to 600V is achieved.
Die Erfindung betrifft einen Energieübertrager (100) zur induktiven Energieübertragung von einem primären Schaltkreis (10) des Energieübertragers (100) an eine erste (5) und eine zweite (15) Spannungsdomäne eines sekundären Schaltkreises (20) des Energieübertragers (100) und zur Informationsübertragung vom sekundären Schaltkreis (20) zum primären Schaltkreis (10). Dabei umfasst der Energieübertrager (100): – einen Transformator (30), über den der primäre Schaltkreis (10) und der sekundäre Schaltkreis (20) induktiv miteinander gekoppelt sind und über den sowohl die Energieübertragung als auch die Informationsübertragung erfolgt; und – ein Amplitudenmodulationsmodul (50) zum Modulieren der Strom- und/oder Spannungsamplitude im sekundären Schaltkreis (20) mit Hilfe eines Amplitudenmodulationsschalters (55), wobei der Amplitudenmodulationsschalter (55) zwischen der ersten (5) und zweiten (15) Spannungsdomäne des sekundären Schaltkreises (20) angeordnet ist und ausgelegt ist, durch Öffnen und Schließen des Amplitudenmodulationsschalters (55) die Strom- und/oder Spannungsamplitude im primären Schaltkreis (10) zu ändern, um somit Information vom sekundären Schaltkreis (20) zum primären Schaltkreis (10) zu übertragen. Die vorliegende Erfindung betrifft ferner einen Gate-Treiber zum Schalten eines Leistungsschalters (500) und ein Verfahren zur induktiven Übertragung von Energie und zur kombinierten Informationsübertragung.
This article covers the design of highly integrated gate drivers and level shifters for high-speed, high power efficiency and dv/dt robustness with focus on automotive applications. With the introduction of the 48 V board net in addition to the conventional 12 V battery, there is an increasing need for fast switching integrated gate drivers in the voltage range of 50 V and above. State-of-the-art drivers are able to switch 50 V in less than 5 ns. The high-voltage electrical drive train demands for galvanic isolated and highly integrated gate drivers. A gate driver with bidirectional signal transmission with a 1 MBit/s amplitude modulation, 10/20 MHz frequency modulation and power transfer over one single transformer will be discussed. The concept of high-voltage charge storing enables an area-efficient fully integrated bootstrapping supply with 70 % less area consumption. EMC is a major concern in automotive. Gate drivers with slope control optimize EMC while maintaining good switching efficiency. A current mode gate driver, which can change its drive current within 10 ns, results in 20 dBuV lower emissions between 7 and 60 MHz and 52 % lower switching loss compared to a conventional constant current gate driver.
Die Erfindung betrifft eine Vorrichtung (100) und ein Verfahren zum elektrischen Verbinden und Trennen zweier elektrischer Potentiale (1, 2). Des Weiteren betrifft die Erfindung eine Verwendung der Vorrichtung (100). Dabei umfasst die Vorrichtung (100): – ein erstes Modul, welches einen ersten und einen zweiten Transistor (10a, 10b) umfasst, wobei der erste Transistor (10a) antiseriell zu dem zweiten Transistor (10b) geschaltet ist; und – ein zweites Modul, welches einen dritten und einen vierten Transistor (10c, 10d) umfasst, wobei der dritte Transistor (10c) antiseriell zu dem vierten Transistor (10d) geschaltet ist; wobei das erste Modul und das zweite Modul parallel geschaltet sind.
More and more power electronics applications utilize GaN transistors as they enable higher switching frequencies in comparison to conventional Si devices. Faster switching shrinks down the size of passives and enables compact solutions in applications like renewable energy, electrical cars and home appliances. GaN transistors benefit from ~10× smaller gate charge QG and gate drive voltages in the range of typically 5V vs. ~15V for Si.
This work presents a fully integrated GaN gate driver in a 180nm HV BCD technology that utilizes high-voltage energy storing (HVES) in an on-chip resonant LC tank, without the need of any external capacitor. It delivers up to 11nC gate charge at a 5V GaN gate, which exceeds prior art by a factor of 45-83, supporting a broad range of GaN transistor types. The stacked LC tank covers an area of only 1.44mm², which corresponds to a superior value of 7.6nC/mm².
This paper presents a fully integrated gate driver in a 180-nm bipolar CMOS DMOS (BCD) technology with 1.5-A max. gate current, suitable for normally OFF gallium nitride (GaN) power switches, including gate-injection transistors (GIT). Full-bridge driver architecture provides a bipolar and three-level gate drive voltage for a robust and efficient GaN switching. The concept of high voltage energy storing (HVES), which comprises an on-chip resonant LC tank, enables a very area-efficient buffer capacitor integration and superior gatedriving speed. It reduces the component count and the influence of parasitic gate-loop inductance. Theory and calculations confirm the benefits of HVES compared to other capacitor implementation methods. The proposed gate driver delivers a gate charge of up to 11.6 nC, sufficient to drive most types of currently available GaN power transistors. Consequently, HVES enables to utilize the fast switching capabilities of GaN for advanced and compact power electronics.
Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ~1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.
The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high speed and power-efficient level shifter for voltages of up to 50V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv / dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40% compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180nm BiCMOS technology. Measurements confirm a 50V 120MHz high-speed operation of the level shifter with a rising / falling propagation delay of 1.45 ns / 1.3 ns, respectively. The dv / dt robustness has been confirmed by measurements for transitions up to 6V/ ns.
Drei Stufen geben Sicherheit
(2018)
GaN-Transistoren bieten ein enormes Potenzial für kompakte Leistungselektronik, indem sie die Größe von passiven Bauelementen verringern. Allerdings bringt das schnelle Schalten Herausforderungen für den Gate-Treiber mit sich. Ein vollständig integrierter Treiber mit drei Spannungsstufen hilft, diese zu lösen.