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Virtual prototyping of integrated mixed-signal smart-sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in combination with a cycle-count accurate temporal decoupling approach to simulate digital components and firmware code execution at high speed while preserving clock cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming communication events. These methods fail in case of non-deterministic, asynchronous events resulting in a possibly invalid simulation result. In this paper, we propose an extension of this method to the case of asynchronous events generated by blackbox sources from which a-priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency and/or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. For an example smart-sensor system model, we show that quasi- periodic events that trigger activities in temporally decoupled processes are handled accurately after the predictor has settled.
Verification of an active time constant tuning technique for continuous-time delta-sigma modulators
(2022)
In this work we present a technique to compensate the effects of R-C / g m -C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with finely tunable circuit structures, such as current-steering digital-to-analog converters (DAC). We apply our technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure, implemented in a 0.35-μm CMOS process. A tuning scheme for the reference currents of the feedback DACs is derived as a function of the individual TC errors and verified by circuit simulations. We confirm the tuning technique experimentally on the fabricated circuit over a TC parameter variation range of ±20%. Stable modulator operation is achieved for all parameter sets. The measured performances satisfy the expectations from our theoretical calculations and circuit-level simulations.
Virtual prototyping of integrated mixed-signal smart sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in conjunction with a cycle-count accurate temporal decoupling approach (TD) to simulate digital components and firmware code execution at high speed while preserving clock-cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming inter-process communication events. These methods fail in the case of non-deterministic, asynchronous events, resulting in potentially invalid simulation results. In this paper, we propose an extension to the case of asynchronous events generated by blackbox sources from which a priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. We analyze the theoretical performance of the presented predictive temporal decoupling approach (PTD) by deriving a cost model that expresses the expected simulation effort in terms of key parameters such as time quantum size and CPU time per simulation cycle. For an exemplary smart-sensor system model, we show that quasi-periodic events that trigger activities in TD processes are handled accurately after the predictor has settled.
Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming tasks of todays complex system on chip (SoC) designs. In contrast to digital system design, AMS designers have to deal with a continuous state space of conservative quantities, highly nonlinear relationships, non-functional influences, etc. enlarging the number of possibly critical scenarios to infinity. In this special session we demonstrate the verification of functional properties using simulative and formal methods. We combine different approaches including automated abstraction and refinement of mixed-level models, state-space discretization as well as affine arithmetic. To reach sufficient verification coverage with reasonable time and effort, we use enhanced simulation schemes to avoid conventional simulation drawbacks.
An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters
(2015)
The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm2. The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm2. This exceeds prior art by a factor of 11.
We propose a novel technique to compensate the effects of R-C / gm-C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with tunable circuit structures, such as current-steering digital-to-analog converters (DAC). This approach constitutes an alternative or supplement to existing compensation techniques, including capacitor or gm tuning. We apply the proposed technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure. A feedback path tuning scheme is derived analytically and confirmed numerically using behavioral simulations. The modulator circuit was implemented in a 0.35-μm CMOS process using an active feedback coefficient tuning structure based on current-steering DACs. Post-layout simulations show that with this tuning structure, constant performance and stable operation can be obtained over a wide range of TC variation.
A fully passive RFID temperature sensor SoC with an accuracy of ±0.4 ◦C (3σ) from 0 ◦C to 125 ◦C
(2019)
This paper presents a fully passive 13.56 -MHz RFID temperature sensor system-on-chip. Its power management unit operates over a large temperature range using a zero temperature coefficient bias source. On-chip temperature sensing is accomplished with low-voltage, low-power CMOS circuitry, and time-domain signal processing. Two readout commands have been defined to study supply noise sensitivity: 1) standard readout, where just a single set of data is transferred to the reader and 2) serial readout, where several sets of data are sent one after the other to the reader. With the standard readout command, the sensor suffers from interference from the RFID command packet and outputs interference as well, while the sensor outputs no interference with the serial readout command. Measurements show that sensor resolution with serial readout is improved by a factor of approximately 16 compared to standard readout. The chip was fabricated in a standard 0.35-μm CMOS technology and chip-on-board mounted to a tuned RFID transponder coil on an aluminum core FR4 PCB substrate. Real time wireless temperature sensing has been demonstrated with a commercial HF RFID reader. With a two-point calibration, the SoC achieves a 3σ sensing accuracy of ±0.4 ◦C from 0◦C to 125 ◦C.
This contribution presents a three-phase power stage for motor control with continuous output voltages using wide bandgap semiconductors and an asynchronous delta-sigma based switching signal generation. The focus of the paper is on an active damping approach for the LC output filter based on inductor current feedback.
Nowadays robust, energy-efficient multisensor microsystems often come with heavily restricted power budgets and the characteristic of remaining in certain states for a longer period of time. During this time frame there is no continuous clock signal required which gives the opportunity to suspend the clock until a new transition is requested. In this paper, we present a new topology for on-demand locally clocked finite state machines. The architecture combines a local adaptive clocking approach with synchronous and asynchronous components forming a quasi synchronous system. Using adaptive and local clocking comes with the advantages of reducing the power consumption while saving design effort when no global clock tree is needed. Combining synchronous and asynchronous components is beneficial compared to previous fully asynchronous approaches concerning the design restrictions. The developed topology is verified by the implementation and simulation of a temperature-ADC sensor system realized in a 180 nm process.
Reduction of power consumption of digital systems is a major concern especially in modern smart sensor systems. These systems are often only activated on request and their power consumption is therefore dominated by the idle-mode. Power reduction mechanisms such as clock or power gating reduce the activity or leakage in the purely digital circuits. We propose a novel adaptive clocking scheme that optimizes the energy demand using a fine-grained oscillator control on cycle-level. To evaluate our new approach, we analytically analyze the power consumption of the regarded system in comparison with available methods. The power of our new adaptive clocking is shown in an integrated smart sensor for capacitive measurements working in a passive wireless sensor node. Using our methods, we show that the energy demand of the example system is reduced even in the case of continuous measurements that demand for a high activity in the digital circuitry.
