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We propose a novel technique to compensate the effects of R-C / gm-C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with tunable circuit structures, such as current-steering digital-to-analog converters (DAC). This approach constitutes an alternative or supplement to existing compensation techniques, including capacitor or gm tuning. We apply the proposed technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure. A feedback path tuning scheme is derived analytically and confirmed numerically using behavioral simulations. The modulator circuit was implemented in a 0.35-μm CMOS process using an active feedback coefficient tuning structure based on current-steering DACs. Post-layout simulations show that with this tuning structure, constant performance and stable operation can be obtained over a wide range of TC variation.
Verification of an active time constant tuning technique for continuous-time delta-sigma modulators
(2022)
In this work we present a technique to compensate the effects of R-C / g m -C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with finely tunable circuit structures, such as current-steering digital-to-analog converters (DAC). We apply our technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure, implemented in a 0.35-μm CMOS process. A tuning scheme for the reference currents of the feedback DACs is derived as a function of the individual TC errors and verified by circuit simulations. We confirm the tuning technique experimentally on the fabricated circuit over a TC parameter variation range of ±20%. Stable modulator operation is achieved for all parameter sets. The measured performances satisfy the expectations from our theoretical calculations and circuit-level simulations.
We present the results of an extensive characterization of the performance and stability of a third-order continuous-time delta-sigma modulator with active coefficient error compensation. Using our previously published coefficient tuning technique, process variation induced R-C time-constant (TC) errors in the forward signal path can be compensated indirectly using continuously tunable DACs in the feedback path. To validate our technique experimentally with a range of real TC variations, we designed a modulator with discretely configurable integration capacitor arrays in a 0.35-μm CMOS process. We configured the capacitors of the fabricated device for a range of total TC variations from -28.4 % to +19.3 % and measured the signal-to-noise ratio (SNR) as a function of the input amplitude before and after compensating the variations electrically using the feedback DACs. The results show that our tuning technique is capable of restoring the desired nominal modulator performance over the entire parameter variation range, including the system’s nominal maximum stable amplitude (MSA).
Nowadays robust, energy-efficient multisensor microsystems often come with heavily restricted power budgets and the characteristic of remaining in certain states for a longer period of time. During this time frame there is no continuous clock signal required which gives the opportunity to suspend the clock until a new transition is requested. In this paper, we present a new topology for on-demand locally clocked finite state machines. The architecture combines a local adaptive clocking approach with synchronous and asynchronous components forming a quasi synchronous system. Using adaptive and local clocking comes with the advantages of reducing the power consumption while saving design effort when no global clock tree is needed. Combining synchronous and asynchronous components is beneficial compared to previous fully asynchronous approaches concerning the design restrictions. The developed topology is verified by the implementation and simulation of a temperature-ADC sensor system realized in a 180 nm process.
Modern wide bandgap power devices promise higher power conversion performance if the device can be operated reliably. As switching speed increases, the effects of parasitic ringing become more prominent, causing potentially damaging overvoltages during device turn-off. Estimating the expected additional voltage caused by such ringing enables more reliable designs. In this paper, we present an analytical expression to calculate the expected overvoltage caused by parasitic ringing based on parasitic element values and operating point parameters. Simulations and measurements confirm that the expression can be used to find the smallest rise time of the switches’ drain-source voltage for minimum overvoltage. The given expression also allows the prediction of the trade off overvoltage amplitude in case of faster required rise times.
Silicon neurons represent different levels of biological details and accuracies as a trade-off between complexity and power consumption. With respect to this trade-off and high similarity to neuron behaviour models, relaxation-type oscillator circuits often yield a good compromise to emulate neurons. In this chapter, two exemplified relaxation-type silicon neurons are presented that emulate neural behaviour with energy consumption under the scale of nJ/spike. The first proposed fully CMOS relaxation SiN is based on mathematical Izhikevich model and can mimic a broad range of physiologically observable spike patterns. The results of kinds of biologically plausible output patterns and coupling process of two SiNs are presented in 0.35 μm CMOS technology. The second type is a novel ultra-low-frequency hybrid CMOS-memristive SiN based on relaxation oscillators and analog memristive devices. The hybrid SiN directly emulates neuron behaviour in the range of physiological spiking frequencies (less than 100 Hz). The relaxation oscillator is implemented and fabricated in 0.13 μm CMOS technology. An autonomous neuronal synchronization process is demonstrated with two relaxation oscillators coupled by an analog memristive device in the measurement to emulate the synchronous behaviour between spiking neurons.