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This paper presents an improvement in usability and integrity of simulation-based analog circuit sizing. Instead of using geometrical sizing parameters (width, length), a transformed design-space, consisting exclusively of electrical parameters (branch currents, efficiencies and speed) is utilized. This design-space is explored more efficiently by optimizers. Moreover, this design-space can be reduced without affecting the quality of the result. The method is illustrated on two application examples, a symmetrical and a miller operational amplifier. Sizing the circuits using the transformed design-space showed significant reduction in required circuit simulations (up to 11x faster), better convergence, without loss in quality.
This paper presents a machine learning powered, procedural sizing methodology based on pre-computed look-up tables containing operating point characteristics of primitive devices. Several Neural Networks are trained for 90nm and 45nm technologies, mapping different electrical parameters to the corresponding dimensions of a primitive device. This transforms the geometric sizing problem into the domain of circuit design experts, where the desired electrical characteristics are now inputs to the model. Analog building blocks or entire circuits are expressed as a sequence of model evaluations, capturing the sizing strategy and intention of the designer in a procedure, which is reusable across different technology nodes. The methodology is employed for the sizing of two operational amplifiers, and evaluated for two technology nodes, showing the versatility and efficiency of this approach.