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A fast transient current-mode buckboost DC-DC converter for portable devices is presented. Running at 1 MHz the converter provides stable 3 V from a 2.7 V to 4.2 V Li-Ion battery. A small voltage under-/overshoot is achieved by fast transient techniques: (1) adaptive pulse skipping (APS) and (2) adaptive compensation capacitance (ACC). The proposed converter was implemented in a 0.25 μm CMOS technology. Load transient simulations confirm the effectiveness of APS and ACC. The improvement in voltage undershoot and response time at light-to-heavy load step (100 mA to 500 mA), are 17 % and 59 %, respectively, in boost mode and 40 % and 49 %, respectively, in buck mode. Similar results are achieved at heavy-to-light load step for overshoot and response time.
While digital IC design is highly automated, analog circuits are still handcrafted in a time-consuming, manual fashion today. This paper introduces a novel Parameterized Circuit Description Scheme (PCDS) for the development of procedural analog schematic generators as parameterized circuits. Circuit designers themselves can use PCDS to create circuit automatisms which capture valuable expert knowledge, offer full topological flexibility, and enhance the re-use of well-established topologies. The generic PCDS concept has been successfully implemented and employed to create parameterized circuits for a broad range of use cases. The achieved results demonstrate the efficiency of our PCDS approach and the potential of parameterized circuits to increase automation in circuit design, also to benefit physical design by promoting the common schematic-driven-layout flow, and to enhance the applicability of circuit synthesis approaches.
In diesem Beitrag wurde gezeigt, wie mit Hilfe von Verfahren zur Analyse von Petri–Netzen ein in der Programmiersprache Kontaktplan erstelltes SPS–Programm analysiert werden kann. Das Ziel des Verfahrens ist dabei nicht eine Verifikation im eigentlichen Sinne sondern das Aufdecken von verbotenen oder unerwünschten Zuständen. Im Beitrag wurden Regeln zur Transformation des im Kontaktplan erstellten Ablaufs in ein Petri–Netz angegeben und anhand der Analyse eines fehlerhaft implementierten Ablaufs die Leistungsfähigkeit des Ansatzes vorgestellt. Das Beispiel zeigt, dass Programmfehler bereits vor einem Test an der realen Anlage erkannt werden können. Bei der weiteren Entwicklung des Verfahrens liegt ein Schwerpunkt auf der Verallgemeinerung auf im Kontaktplan entwickelte Programmorganisationseinheiten, die nicht nur reine
Abläufe implementieren. Ein weiterer wichtiger Entwicklungsschritt ist die graphische Unterstützung der Fehlersuche im Erreichbarkeitsgraphen, so dass insgesamt ein leistungsfähiges Werkzeug zur Unterstützung der Implementierung von Ablaufsteuerungen im Kontaktplan zur Verfügung steht.
IGBT modules with anti-parallel FWDs are widely used in inductive load switching power applications, such as motor drive applications. Nowadays there is a continuous effort to increase the efficiency of such systems by decreasing their switching losses. This paper addresses the problems arising in the turn-on process of an IGBT working in hard-switching conditions. A method is proposed which achieves – contrary to most other approaches – a high switching speed and, at the same time, a low peak reverse-recovery current. This is done by applying an improved gate current waveform that is briefly lowered during the turn-on process. The proposed method achieves low switching losses. Its effectiveness is demonstrated by experimental results with IGBT modules for 600V and 1200V.
Advanced power semiconductors such as DMOS transistors are key components of modern power electronic systems. Recent discrete and integrated DMOS technologies have very low area-specific on-state resistances so that devices with small sizes can be chosen. However, their power dissipation can sometimes be large, for example in fault conditions, causing the device temperature to rise significantly. This can lead to excessive temperatures, reduced lifetime, and possibly even thermal runaway and subsequent destruction. Therefore, it is required to ensure already in the design phase that the temperature always remains in an acceptable range. This paper will show how self-heating in DMOS transistors can be experimentally determined with high accuracy. Further, it will be discussed how numerical electrothermal simulations can be carried out efficiently, allowing the accurate assessment of self-heating within a few minutes. The presented approach has been successfully verified experimentally for device temperatures exceeding 500 ◦C up to the onset of thermal runaway.
This paper presents a new broadband antenna for satellite communications. It describes the procedure involved in the design of a microstrip antenna array and its multi-level passive feed network that together yield circular polarization and the necessary gain to be used in an earth-satellite link. The designed antenna is notable for its large bandwidth, circular polarization, high gain and small dimensions.
This paper presents the design and simulation processes of an Equiangular Spiral Antenna for the extremely high frequencies between 65 GHz and 170 GHz. A new approach for the analysis of the antenna’s electrical parameters is described. This approach is based on formalism proposed by Rumsey to determine the EM field produced by an equiangular spiral antenna. Analytical expressions of the electrical parameters such as the gain or the directivity are then calculated using well sustained mathematical approximations. The comparison of obtained results with those from numerical integration methods shows a good agreement.
DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.
To improve the energy conversion efficiency of solar organic cells, the clue may lie in the development of devices inspired by an efficient light harvesting mechanism of some aquatic photosynthetic microorganisms that are adapted to low light intensity. Consequently, we investigated the pathways of excitation energy transfer (EET) from successive light harvesting pigments to the low energy level inside the phycobiliprotein antenna system of Acaryochloris marina, a cyanobacterium, using a time resolved absorption difference spectroscopy with a resolution time of 200 fs. The objective was to understand the actual biochemical process and pathways that determine the EET mechanism. Anisotropy of the EET pathway was calculated from the absorption change trace in order to determine the contribution of excitonic coupling. The results reveal a new electron energy relaxation pathway of 14 ps inside the phycocyanin component, which runs from phycocyanin to the terminal emitter. The bleaching of the 660 nm band suggests a broader absorption of the terminal emitter between 660 nm and 675 nm. Further, there are trimer depolarization kinetics of 450 fs and 500 fs in high and low ionic strength, respectively, which arise from the relaxation of the β84 and α84 in adjacent monomers of phycocyanin. Under conditions of low ionic strength buffer solution, the evolution of the kinetic amplitude during the depolarization of the trimer is suggestive of trimer conservation within the phycocyanin hexamer. The anisotropy values were 0.38 and 0.40 in high and in low ionic strength, respectively, indicating that there is no excitonic delocalization in the high energy level of phycocyanin hexamers.
We investigated the excitation modes of the light-harvesting protein phycocyanin (PC) from Thermosynechococcus vulcanus in the crystalline state using UV and near-infrared Raman spectroscopy. The spectra revealed the absence of a hydrogen out-of-plane wagging (HOOP) mode in the PC trimer, which suggests that the HOOP mode is activated in the intact PC rod, while it is not active in the PC trimer. Furthermore, in the PC trimer an intense mode at 984 cm−1 is assigned to the C–C stretching vibration while the mode at 454 cm−1 is likely due to ethyl group torsion. In contrast, in the similar chromophore phytochromobilin the C5,10,15-D wag mode at 622 cm−1 does not come from a downshift of the HOOP. Additionally, the absence of modes between 1200 and 1300 cm−1 rules out functional monomerization. A correlation between phycocyanobilin (PCB) and phycoerythrobilin (PEB) suggests that the PCB cofactors of the PC trimer appear in a conformation similar to that of PEB. The conformation of the PC rod is consistent with that of the allophycocyanin (APC) trimer, and thus excitonic flow is facilitated between these two independent light harvesting compounds. This excitonic flow from the PC rod to APC appears to be modulated by the vibration channels during HOOP wagging, C = C stretching, and the N–H rocking in-plan vibration.
In visual adaptive tracking, the tracker adapts to the target, background, and conditions of the image sequence. Each update introduces some error, so the tracker might drift away from the target over time. To increase the robustness against the drifting problem, we present three ideas on top of a particle filter framework: An optical-flow-based motion estimation, a learning strategy for preventing bad updates while staying adaptive, and a sliding window detector for failure detection and finding the best training examples. We experimentally evaluate the ideas using the BoBoT dataseta. The code of our tracker is available online.
The capability of the method of Immersion transmission ellipsometry (ITE) (Jung et al. Int Patent WO, 2004/109260) to not only determine three-dimensional refractive indices in anisotropic thin films (which was already possible in the past), but even their gradients along the z-direction (perpendicular to the film plane) is investigated in this paper. It is shown that the determination of orientation gradients in deep-sub-lm films becomes possible by applying ITE in combination with reflection ellipsometry. The technique is supplemented by atomic force microscopy for measuring the film thickness. For a photooriented thin film, no gradient was found, as expected. For a photo-oriented film, which was subsequently annealed in a nematic liquid crystalline phase, an order was found similar to the one applied in vertically aligned nematic displays, with a tilt angle varying along the z-direction. For fresh films, gradients were only detected for the refractive index perpendicular to the film plane, as expected.
DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures, which can lead to device failure and reduced lifetime. Hence, it must be ensured that the device temperature does not rise too much. For this, the influence of the on-chip metallization must be taken into account because of the good thermal conductivity and significant thermal capacitance of the metal layers on top of the active DMOS area. In this paper, test structures with different metal layers and vias configurations are presented that can be used to determine the influence of the onchip metallization on the temperature caused by self-heating. It will be shown how accurate results can be obtained to determine even the influence of small changes in the metallization. The measurement results are discussed and explained, showing how on-chip metallization helps to lower the device temperature. This is further supported by numerical simulations. The obtained insights are valuable for technology optimization, but are also useful for calibration of temperature simulators.
Bionic optimisation is one of the most popular and efficient applications of bionic engineering. As there are many different approaches and terms being used, we try to come up with a structuring of the strategies and compare the efficiency of the different methods. The methods mostly proposed in literature may be classified into evolutionary, particle swarm and artificial neural net optimisation. Some related classes have to be mentioned as the non-sexual fern optimisation and the response surfaces, which are close to the neuron nets. To come up with a measure of the efficiency that allows to take into account some of the published results the technical optimisation problems were derived from the ones given in literature. They deal with elastic studies of frame structures, as the computing time for each individual is very short. General proposals, which approach to use may not be given. It seems to be a good idea to learn about the applicability of the different methods at different problem classes and then do the optimisation according to these experiences. Furthermore in many cases there is some evidence that switching from one method to another improves the performance. Finally the identification of the exact position of the optimum by gradient methods is often more efficient than long random walks around local maxima.
Enhancing the undergraduate educational experience : development of a micro-gas turbine laboratory
(2014)
A Capstone C30 MicroTurbine has been installed, instrumented, and utilized in a junior-level laboratory course at Valparaiso University. The C30 MicroTurbine experiment enables Valparaiso University to educate students interested in power generation and turbine technology. The first goal of this experiment is for students to explore a gas turbine generator and witness the discrepancies between idealized models and real thermodynamic systems. Secondly, students measure and analyze data to determine where losses occur in a real gas turbine. The third educational goal is for students to recognize the true costs associated with natural gas use, i.e. the hidden costs of transporting the gas to the consumer. Overall, the gas turbine experiment has garnered positive feedback from students. The twenty-six students who performed the lab in Spring 2014 rated the quality and usefulness of the gas turbine experiment as 4.28 and 4.19, respectively, on a 1-5 Likert scale, where 1 is low and 5 is high.
Since November 2011 the standard DIN 4709 stipulates performance tests for Micro-CHP units in Germany. In contrast to steady state measurements of the CHP unit itself, the test according to DIN 4709 includes the thermal storage tank as well as the internal control unit, and it is based on a 24 h test cycle following a specified thermal load profile. Hence, heat losses from the storage tank are as well taken into account as transient losses of the CHP unit. In addition, the control strategy for loading and unloading the storage tank affects the test results.
The DIN 4709 test cycle has been applied at the test stand for Micro-CHP units at Reutlingen University, and results for the Micro-CHP unit WhisperGen and the EC Power units XRGI 15® and XRGI 20® are available. During the analysis a method has been developed to evaluate the results in case the test cycle does not end in a time slot between 24 and 24.5 h after the starting as demanded by DIN 4709. Since this method has been successfully applied to the test of various CHP units of different size and technology so far, it is suggested to incorporate it to DIN 4709 during the next revision of the standard.
The performance numbers obtained reveal the differences in efficiencies measured at steady-state on the one hand and following the DIN 4709 test cycle on the other hand. While the deviations in electrical efficiencies are small, thermal efficiencies according to DIN 4709 fall below steady state data by 3–6 percentage points. This is attributed to transient thermal losses and heat losses from the storage tank, which are not included in steady state and separate testing of the CHP unit, only.
Compared to diesel or gasoline, using compressed natural gas as a fuel allows for significantly decreased carbon dioxide emissions. With the benefits of this technology fully exploited, substantial increases of engine efficiency can be expected in the near future. However, this will lead to exhaust gas temperatures well below the range required for the catalytic removal of residual methane, which is a strong greenhouse gas. By combination with a countercurrent heat exchanger, the temperature level of the catalyst can be raised significantly in order to achieve sufficient levels of methane conversion with minimal additional fuel penalty. This thesis provides fundamental theoretical background of these so-called heat-integrated exhaust purification systems. On this basis, prototype heat exchangers and appropriate operating strategies for highly dynamic operation in passenger cars are developed and evaluated.
A millimeter-wave power amplifier concept in an advanced silicon germanium (SiGe) BiCMOS technology is presented. The goal of the concept is to investigate the impact of physical limitations of the used heterojunction bipolar transistors (HBT) on the performance of a 77 GHz power amplifier. High current behavior, collectorbase breakdown and transistor saturation can be forced with the presented design. The power amplifier is manufactured in an advanced SiGe BiCMOS technology at Infineon Technologies AG with a maximum transit frequency fT of around 250 GHz for npn HBT’s [1]. The simulation results of the power amplifier show a saturated output power of 16 dBm at a power added efficiency of 13%. The test chip is designed for a supply voltage of 3.3 V and requires a chip size of 1.448 x 0.930 mm².
Nowadays the software development plays an important role in the entire value chain in production machine and plant engineering. An important component for rapid development of high quality software is the virtual commissioning. The real machine is described on the basis of simulation models. Therefore, the control software can be verified at an early stage using the simulation models. Since production machines are produced highly individual or in very small series, the challenge of virtual commissioning is to reduce the effort to the development of simulation models. Therefore, a systematic reuse of the simulation models and the control software for different variants of a machine is essential for an economic use. This necessarily requires a consideration of the variability which may occur between the production machines. This paper analyzes the question of how to systematically deal with the software-related variability in the context of virtual commissioning. For this purpose, first the characteristics of the virtual commissioning and variability handling are considered. Subsequently, the requirements to a so-called variant infrastructure for virtual commissioning are analyzed and possible solutions are discussed.
Today’s cars are characterized by many functional variants. There are many reasons for the underlying variability, from the adaptation to diverse markets to different technical aspects, which are based on a cross platform reuse of software functions. Inevitably, this variability is reflected in the model-based automotive software development. A modeling language, which is widely used for modeling embedded software in the automotive industry, is MATLAB/Simulink. There are concepts facing the high demand for a systematic handling of variability in Simulinkmodels. However, not every concept is suitable for every automotive application. In order to present a classification of concepts for modeling variability in Simulink, this paper first has to determine the relevant use cases for variant handling in modelbased automotive software development. Existing concepts for modeling variability in Simulink will then be presented before being classified in relation to the previously determined use cases.
Bootstrap circuits are mainly used for supplying a gate driver circuit to provide the gate overdrive voltage for a high-side NMOS transistor. The required charge has to be provided by a bootstrap capacitor which is often too large for integration if an acceptable voltage dip at the capacitor has to be guaranteed. Three options of an area efficient bootstrap circuit for a high side driver with an output stage of two NMOS transistors are proposed. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and connected when the gate driver turns on. A high voltage swing at the second capacitor leads to a high charge allocation. Both bootstrap capacitors require up to 70% less area compared to a conventional bootstrap circuit. This enables compact power management systems with fewer discrete components and smaller die size. A calculation guideline for optimum bootstrap capacitor sizing is given. The circuit was manufactured in a 180nm high-voltage BiCMOS technology as part of a high-voltage gate driver. Measurements confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit including two stacked 75.8pF and 18.9pF capacitors results in a voltage dip lower than 1V. This matches well with the theory of the calculation guideline.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. This leads especially at a high input voltage to a decreasing efficiency caused by switching losses. Conventional calculations are not suitable to predict the efficiency as parasitic capacitances have a significant loss contribution. This paper presents an analytical efficiency model which considers parasitic capacitances separately and calculates the power loss contribution of each capacitance to any resistive element. The proposed model is utilized for efficiency optimization of converters with switching frequencies >10MHz and input voltages up to 40V. For experimental evaluation a DCDC converter was manufactured in a 180 nm HV BiCMOS technology. The model matches a transistor level simulation and measurement results with an accuracy better than 3.5 %. The accuracy of the parasitic capacitances of the high voltage transistor determines the overall accuracy of the efficiency model. Experimental capacitor measurements can be fed into the model. Based on the model, different architectures have been studied.
An improved gate drive circuit is provided for a power device, such as a transistor. Tue gate driver circuit may in -clude: a current control circuit; a first secondary current source that is used to control the switching transient during turn off of the power transistor and a second secondary current source that is used to control the switching transient during turn on of the power transistor. In operation, the current control circuit operates, during turn on ofthe power transistor, to source a gate drive current to a control node ofthe power transistor and, during turn off ofthe power transistor, to sink a gate drive current from the control node of the power transistor. The first and second secondary current sources adjust the gate drive current to control the voltage or current rate of change and thereby the overshoot during the switching transient.
An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters
(2015)
The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm2. The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm2. This exceeds prior art by a factor of 11.
Virtual prototyping of integrated mixed-signal smart-sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in combination with a cycle-count accurate temporal decoupling approach to simulate digital components and firmware code execution at high speed while preserving clock cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming communication events. These methods fail in case of non-deterministic, asynchronous events resulting in a possibly invalid simulation result. In this paper, we propose an extension of this method to the case of asynchronous events generated by blackbox sources from which a-priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency and/or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. For an example smart-sensor system model, we show that quasi- periodic events that trigger activities in temporally decoupled processes are handled accurately after the predictor has settled.
Modern power DMOS transistors greatly benefit from the continuous advances of the technology, which yield devices with very low area-specific RDS,on figures of merit and therefore allow for significantly reduced active areas. However, in many applications, where the devices must dissipate high amounts of energy and thus are subjected to significant self-heating, the active area is not dictated by RDS,on requirements, but by the energy constraints. In this paper, a simple method of improving the energy capability and reliability of power DMOS transistors operating in pulsed conditions is proposed and experimentally verified. The method consists in redistributing the power density from the hotter to the cooler device regions, hence achieving a more homogeneous temperature distribution and a reduced peak temperature. To demonstrate the principle, a simple gate offset circuit is used to redistribute the current density to the cooler DMOS parts. No technology changes are needed for the implementation, only minor changes to the driver circuit are necessary, with a minimal impact on the additional required active area. Improvements in the energy capability from 9.2% up to 39% have been measured. Furthermore, measurements have shown that the method remains effective also if the operating conditions change significantly. The simplicity and the effectiveness of the implementation makes the proposed method suitable to be used in a wide range of applications.
The paper illustrates the status quo of a research project for the development of a control system enabling CHP units for a demand-oriented electricity production by an intelligent management of the heat storage tank. Thereby the focus of the project is twofold. One is the compensation of the fluctuating power production by the renewable energies solar and wind. Secondly, a reduction of the load on the power grid is intended by a better match of local electricity demand and production. In detail, the general control strategy is outlined, the method utilized for forecasting heat and electricity demand is illustrated as well as a correlation method for the temperature distribution in the heat storage tank based on a Sigmoid function is proposed. Moreover, the simulation model for verification and optimization of the control system and the two field test sites for implementing and testing the system are introduced.
For area reasons, NMOS transistors are preferred over PMOS for the pull-up path in gate drivers. Bootstrapping has to ensure sufficient NMOS gate overdrive. Especially in high-current gate drivers with large transistors, the bootstrap capacitor is too large for integration. This paper proposes three options of fully integrated bootstrap circuits. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and ensures high charge allocation when the driver turns on. A capacitor sizing guideline and the overall driver implementation including a suitable charge pump for permanent driver activation is provided. A linear regulator is used for bootstrap supply and it also compensates the voltage drop of the bootstrap diode. Measurements from a testchip in 180 nm high-voltage BiCMOS confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit with two stacked 75.8 pF and 18.9 pF capacitors results in an expected voltage dip of lower than 1 V. Both bootstrap capacitors require 70% less area compared to a conventional bootstrap circuit. Besides drivers, the proposed bootstrap can also be directly applied to power stages to achieve fully integrated switched mode power supplies or class-D output stages.
Equations for fast and exact calculation of a simple model for heat transfer from a bond wire to a cylindrical finite mold package including nonideal heat transfer from wire to mold are presented. These allow for a characterization of an arbitrary mold/bond wire combination. The real mold geometry is approximated using the mold model cylinder radius and the thermal contact conductance of the mold/bond wire interface. For changes in bond and mold material, wire length, diameter, and current transient profiles, the resulting temperature transients can then be predicted. As the method is based on numerical integration of differential equations, arbitrary pulse shapes, which are industrially relevant, can be calculated. Very high thermal contact conductance values (above 40 000 W/m2K heat transfer) have been detected in real package/bond systems. The method was validated by successful comparison with finite element method simulations and alternative calculation methods and measurements.
To prevent high buildings in endangered zones suffering from seismic attack, TMD are applied successfully. In many applications the dampers are placed along the height of the edifice to reduce the damage during the earthquake. The dimensioning of TMD is a multidimensional optimisation problem with many local maxima. To find the absolute best or a very good design, advanced optimisation strategies have to be applied. Bionic optimization proposes different methods to deal with such tasks but requires many repeated studies of the buildings and dampers design. To improve the speed of the analysis, the authors propose a reduced model of the building including the dampers. A series of consecutive generations shows a growing capacity to reduce the impact of an earthquake on the building. The proposals found help to dimension the dampers. A detailed analysis of the building under earthquake loading may yield an efficient design.
Large power semiconductors are complex structures, their metallization usually containing many thousands of contacts or vias. Because of this, detailed FEM simulations of the whole device are nowadays not possible because of excessive simulation time.
This paper introduces a simulation approach which allows quick identification of critical regions with respect to lifetime by a simplified simulation. For this, the complex layers are replaced by a much simpler equivalent layer, allowing a simulation of the whole device even including its package. In a second step, precise simulations taking all details of the structure into account are carried out, but only for the critical regions of interest. Thus, this approach gives detailed results where required with consideration of the whole structure including packaging. Further, the simulation time requirements are very moderate.
DMOS transistors in integrated smart power technologies are often subject to cyclic power dissipation with substantial selfheating. This leads to repetitive thermo mechanical stress, causing fatigue of the on-chip metallization and limiting the lifetime. Hence, most designs use large devices for lower peak temperatures and thus reduced stress to avoid premature failures.
However, significantly smaller DMOS transistors are acceptable if the system reverts to a safer operating condition with lower stress when a failure is expected to occur in the near future. Hence, suitable early-warning sensors are required. This paper proposes a floating metal meander embedded between DMOS source and drain to detect an impending metallization failure. Measurement results of several variants will be presented and discussed, investigating their suitability as early warning indicators.
An experimental study of a zero voltage switching SiC boost converter with an active snubber network
(2015)
This paper presents a quasi-resonant, zero voltage switching (ZVS) SiC boost converter for an output power of up to 10 kW. The converter is realized with an easily controllable active snubber network that allows a reduction of switching losses by minimizing the voltage stress applied to the active switch. With this approach, an increase of the switching frequency is possible, allowing a reduction of the system size. Experiments show a maximum converter efficiency up to 99.2% for a switching frequency of 100 kHz. A second version of the converter enables a further size reduction by increasing the switching frequency to 300 kHz while still reaching a high efficiency up to 98.4 %.
This paper evaluates experimentally the susceptibility of IT-networks under influences and the threats of HPEM (High Power Electromagnetic) and IEMI (Intentional Electromagnetic Interferences). As HPEM source a PBG 5 (Pulse Burst Generator) adapted to a TEM (Transversal Electromagnetic) Horn type antenna and a 90 cm IRA (Impulse Radiating Antenna) type antenna is used. Different network cable types and categories with different lengths are used. The immunity of the IT network is examined and the breakdown failure rate of the system is defined for a PRF (Pulse Repetition Frequency) of 500 s-1 in duration of 10 seconds. Series of measurements were carried out and disturbances of keyboards, mouse, switches, distortions on monitors and failures of the IT network and, even crash of PCs were observed. It is shown amongst other that by increasing the pulse repetition rate or frequency, generic test IT-networks are more susceptible to interference. Obtained results provide another view of the susceptibility analysis of modern generic IT-networks against UWB-Threats.
The possibility to bring the interference source, close to the potential target is characterized by the property of the source as stationary, portable, mobile, very mobile and highly mobile [3]. Starting from the existing and well-known IEME interference or IEMI (Intentional Electromagnetic Interference) and the already existing classifications an analysis of methods based on a comparative study of the methods used to classify the intentional EM environment is carried out, which takes into account the frequency, the cost, the amplitude of the noise signal, the radiated power and the energy of a pulse of radiation.
In this paper, we propose a novel fitting method that uses local image features to fit a 3D morphable face model to 2D images. To overcome the obstacle of optimising a cost function that contains a non-differentiable feature extraction operator, we use a learning-based cascaded regression method that learns the gradient direction from data. The method allows to simultaneously solve for shape and pose parameters. Our method is thoroughly evaluated on morphable model generated data and first results on real data are presented. Compared to traditional fitting methods, which use simple raw features like pixel colour or edge maps, local features have been shown to be much more robust against variations in imaging conditions. Our approach is unique in that we are the first to use local features to fit a 3D morphable model. Because of the speed of our method, it is applicable for realtime applications. Our cascaded regression framework is available as an open source library at github.com/patrikhuber/ superviseddescent.
This book shows how the objectification orientated controlling approach can ensure the successful management of a company in a challenging and competitive environment, which is characterized by increasing complexity, dynamic, and uncertainty. The objectification orientated controlling approach outlined in this book is based on the philosophy of a service provider who supports managers and decision-makers. This idea is well-reflected in the term "business partner", which shows that only management and controlling together are able to ensure the success of a company. The author combines scientific and practical evidence to deduce the objectification orientated controlling approach. The challenges of globalization, a stringent alignment at company value, as well as the objectification approach are the main building blocks. Based on these criteria for success, the controlling approach can be individually shaped for each specific company. This book is aimed at students and practitioners who want to learn more about improving business using a state-of-the-art support function, controlling.
DMOS transistors often suffer from substantial self-heating during high power dissipation, which can lead to thermal destruction if the device temperature reaches excessive values. A successfully demonstrated method to reduce the peak temperature is the redistribution of power dissipation density from the hotter to the cooler device areas by careful layout modification. However, this is very tedious and time-consuming if complex-shaped devices as often found in industrial applications are considered.
This paper presents an approach for fully automatic layout optimization which requires only a few hours processing time. The approach is applied to complex shaped test structures which are investigated by measurements and electro-thermal simulations. Results show a significantly lower peak temperature and an energy capability gain of 84 %, offering potential for a 18 % size reduction of active area.
This paper presents a measurement setup and an assembly technique suitable for characterization of power semiconductor devices under very high temperature conditions exceeding 500°C. An important application of this is the experimental investigation of wide bandgap semiconductors. Measurement results are shown for a 1200V SiC MOSFET and a 650V depletion mode GaN HEMT.
A TLP system with a very low characteristic impedance of 1.5 Ω and a selectable pulse length from 0.5 to 6 μs is presented. It covers the entire operation region of many power semiconductors up to 700 V and 400 A. Ist applicability is demonstrated by determining the Output characteristics for two Cool MOS devices up to destruction.
The experimental characterization of the thermal impedance Zth of large power MOSFETs is commonly done by measuring the junction temperature Tj in the cooling phase after the device has been heated, preferably to a high junction temperature for increased accuracy. However, turning off a large heating current (as required by modern MOSFETs with low on-state resistances) takes some time because of parasitic inductances in the measurement system. Thus, most setups do not allow the characterization of the junction temperature in the time range below several tens of μs.
In this paper, an optimized measurement setup is presented which allows accurate Tj characterization already 3 μs after turn-off of heating. With this, it becomes possible to experimentally investigate the influence of thermal capacitances close to the active region of the device. Measurement results will be presented for advanced power MOSFETs with very large heating currents up to 220 A. Three bonding variants are investigated and the observed differences will be explained.
Automated stabilization of loading capacity of coal shearer screw with controlled cutting drive
(2015)
A solution of topical scientific problem of coal shearer output increase providing minimum specific power supply for coal cutting, transportation, and loading in terms of thin seams has been proposed. The solution is based on the use of earlier proposed criterion of screw gumming for optimum cutting velocity-coal shearer feed rate ratio in the context of increased screw rotation owing to phase voltage frequency increase. Simulation results of automated control system for coal shearer operations with frequency-controlled cutting drive within thin seams have confirmed the efficiency of the system using proposed algorithm of smart analysis of coal shearer power signal.
This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125 ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30%by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2A load. The peak efficiency is 81 %.
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum conversion ratio are limited by the duty cycle of a PWM signal. In DCDC converters, a sawtooth generator is the fundamental circuit block to generate the PWM signal. The presented PWM generator is based on two parallel, fully interleaved PWM generator stages, each containing an integrator based sawtooth generator and two 3-stage highspeed comparators. A digital multiplexing of the PWM signals of each stage eliminates the dependency of the minimum on-time on the large reset times of the sawtooth ramps. A separation of the references of the PWM comparators in both stage allows to configure the PWM generator for a DCDC converter operating in fixed frequency or in constant on-time mode, which requires an operation in a wide frequency range. The PWM generator was fabricated in an 180 nm HV BiCMOS technology, as part of a DCDC converter. Measurements confirm minimum possible ontime pulses as short as 2 ns and thus allows switching frequencies of DCDC converters of >50 MHz at small duty cycle of <10%. At moderate duty cycles switching frequencies up to 100 MHz are possible.
Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500 ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
Socially interactive robots with human-like speech synthesis and recognition, coupled with humanoid appearance, are an important subject of robotics and artificial intelligence research. Modern solutions have matured enough to provide simple services to human users. To make the interaction with them as fast and intuitive as possible, researchers strive to create transparent interfaces close to human-human interaction. Because facial expressions play a central role in human-human communication, robot faces were implemented with varying degrees of human-likeness and expressiveness. We propose a way to implement a program that believably animates changing facial expressions and allows to influence them via inter-process communication based on an emotion model. This will can be used to create a screen based virtual face for a robotic system with an inviting appearance to stimulate users to seek interaction with the robot.
When a bonding wire becomes too hot, it fuses and fails. The ohmic heat that is generated in the wire can be partially dissipated to a mold package. For this cooling effect the thermal contact between wire and package is an important parameter. Because this parameter can degrade over lifetime, the fusing of a bonding wire can also occur as a long-term effect. Another important factor is the thermal power generated in the vicinity of the bond pads. Nowadays, the reliability of bond wires relies on robust dimensioning based on estimations. Smaller package sizes increase the need for better predictive methods.
The Bond Calculator, a new thermo-electrical simulation tool, is able to predict the temperature profiles along bond wires of arbitrary dimensions in dependence on the applied arbitrary transient current profile, the mold surrounding the wire, and the thermal contact between wire and mold.
In this paper we closely investigated the spatial temperature profiles along different bond wires in air in order to make a first step towards the experimental verification of the simulation model. We are using infrared microscopy in order to measure the thermal radiation generated along the bond wire. This is easier to perform quantitatively in air than in the mold package, because of the non-negligible absorbance of the mold material in the infrared wavelength region.
In practice, the use of layout PCells for analog IC design has not advanced beyond primitive devices and simple modules. This paper introduces a Constraint-Administered PCell-Applying Blocklevel Layout Engine (CAPABLE) which permits PCells to access their context, thus enabling a true "bottom-up" development of complex parameterized modules. These modules are integrated into the design flow with design constraints and applied by an execution cockpit via an automatically built layout script. The practical purpose of CAPABLE is to easily generate full-custom block layouts for given schematic circuits. Perspectively, our results inspire a whole new conception of PCells that can not only act (on demand), but also react (to environmental changes) and interact (with each other).