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Advanced power semiconductors such as DMOS transistors are key components of modern power electronic systems. Recent discrete and integrated DMOS technologies have very low area-specific on-state resistances so that devices with small sizes can be chosen. However, their power dissipation can sometimes be large, for example in fault conditions, causing the device temperature to rise significantly. This can lead to excessive temperatures, reduced lifetime, and possibly even thermal runaway and subsequent destruction. Therefore, it is required to ensure already in the design phase that the temperature always remains in an acceptable range. This paper will show how self-heating in DMOS transistors can be experimentally determined with high accuracy. Further, it will be discussed how numerical electrothermal simulations can be carried out efficiently, allowing the accurate assessment of self-heating within a few minutes. The presented approach has been successfully verified experimentally for device temperatures exceeding 500 ◦C up to the onset of thermal runaway.
DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.
DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures, which can lead to device failure and reduced lifetime. Hence, it must be ensured that the device temperature does not rise too much. For this, the influence of the on-chip metallization must be taken into account because of the good thermal conductivity and significant thermal capacitance of the metal layers on top of the active DMOS area. In this paper, test structures with different metal layers and vias configurations are presented that can be used to determine the influence of the onchip metallization on the temperature caused by self-heating. It will be shown how accurate results can be obtained to determine even the influence of small changes in the metallization. The measurement results are discussed and explained, showing how on-chip metallization helps to lower the device temperature. This is further supported by numerical simulations. The obtained insights are valuable for technology optimization, but are also useful for calibration of temperature simulators.
Modern power DMOS transistors greatly benefit from the continuous advances of the technology, which yield devices with very low area-specific RDS,on figures of merit and therefore allow for significantly reduced active areas. However, in many applications, where the devices must dissipate high amounts of energy and thus are subjected to significant self-heating, the active area is not dictated by RDS,on requirements, but by the energy constraints. In this paper, a simple method of improving the energy capability and reliability of power DMOS transistors operating in pulsed conditions is proposed and experimentally verified. The method consists in redistributing the power density from the hotter to the cooler device regions, hence achieving a more homogeneous temperature distribution and a reduced peak temperature. To demonstrate the principle, a simple gate offset circuit is used to redistribute the current density to the cooler DMOS parts. No technology changes are needed for the implementation, only minor changes to the driver circuit are necessary, with a minimal impact on the additional required active area. Improvements in the energy capability from 9.2% up to 39% have been measured. Furthermore, measurements have shown that the method remains effective also if the operating conditions change significantly. The simplicity and the effectiveness of the implementation makes the proposed method suitable to be used in a wide range of applications.
The loss contribution of a 2.3kW synchronous GaN-HEMT boost converter for an input voltage of 250V and an output voltage of 500V was analyzed. A simulation model which consists of two parts is introduced. First, a physics-based model is used to determine the switching losses. Then, a system simulation is applied to calculate the losses of the specific elements. This approach allows a fast and accurate system evaluation as required for further system optimization.
In this work, a hard- and a zero-voltage turn-on switching converter are compared. Measurements were performed to verify the simulation model, showing a good agreement. A peak efficiency of 99% was achieved for an output power of 1.4kW. Even with an output power above 400W, it was possible to obtain a system efficiency exceeding 98 %.
Influence of metallization layout on aging detector lifetime under cyclic thermo-mechanical stress
(2016)
The influence of the layout on early warning detectors in BCD technologies for metallization failure under cyclic thermo-mechanical stress was investigated. Different LDMOS transistors, with narrow or wide metal fingers and with or without embedded detectors, were used. The test structures were repeatedly stressed by pronounced self-heating until failure (a short circuit) was detected. The results show that the layout of the on-chip metallization has a large impact on the lifetime. A significant influence of the detectors on the lifetime was also observed, in our case causing a reduction of more than a factor of two, but only for the test structure with narrow metal fingers. The experimental results are explained by an efficient numerical thermo mechanical simulation approach, giving detailed insights into the strain distribution in the metal system. These results are important for aging detector design and, morever, for LDMOS on-chip metal layout in general.
In many automotive applications, repetitive selfheating is the most critical operation condition for LDMOS transistors in smart power ICs. This is attributed to thermomechanical stress in the on-chip metallization, which results from the different thermal expansion coefficients of the metal and the intermetal dielectric. After many cycles, the accumulated strain in the metallization can lead to short circuits, thus limiting the lifetime. Increasing the LDMOS size can help to lower peak temperatures and therefore to reduce the stress. The downside of this is a higher cost. Hence, it has been suggested to use resilient systems that monitor the LDMOS metallization and lower the stress once a certain level of degradation is reached. Then, lifetime requirements can be fulfilled without oversizing LDMOS transistors, even though a certain performance loss has to be accepted. For such systems, suitable sensors for metal degradation are required. This work proposes a floating metal line embedded in the LDMOS metallization. The suitability of this approach has been investigated experimentally by test structures and shown to be a promising candidate. The obtained results will be explained by means of numerical thermo-mechanical simulations.
This work investigates the electro-thermal behavior and failure mechanism of a 600V depletion-mode GaN HEMT by experimental analysis and numerical thermal simulations. For this device, the positive temperature coefficient of the draingate leakage current can lead to the formation of hot spots. This localized thermal runaway which ultimately results in a breakdown of the inherent drain-gate junction is found to be the dominant cause of failure.
This paper presents an efficient implementation of a reconfigurable battery stack which allows full exploitation of the capacity of every single cell. Contrary to most other approaches, it is possible to electrically remove one or more cells from the battery stack. Therefore, the overall capacity of the system is not restricted by the weaker cells, and cells with very different states of health can be used, making the system very attractive for refurbished batteries. For the required switches, low-voltage high-current MOSFETs are used. A demonstrator has been built with a total capacity of up to 3.5 kWh, a nominal voltage of 35 V, and currents up 200 A.
This paper presents a compact 3 kW bidirectional GaN-HEMT DC/DC converter for 360V to 400-500 V. A very high efficiency has been reached by applying a zero voltage turn-on in conjunction with a negative gate-source voltage, even though normally-off HEMTs are used. Further improvements were achieved by adapting the switching frequency to the load current and output voltage, as will be explained by means of the loss contribution of the specific elements for a constant and an adaptive switching frequency. Measurements have shown a high converter efficiency exceeding 99% over a wide output power range of up to 3 kW.