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This paper presents a dc–dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc–dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130 nm CMOS technology with an area of only 0.14 mm². It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.
This paper presents a wide-Vin step-down parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300-nH resonant coil, placed in parallel to a conventional buck converter. Soft-switching resonant converters are beneficial for high-Vin multi-MHz converters to reduce dominant switching losses, enabling higher switching frequencies. The output filter inductor is optimized based on an empirical study of available inductors. The study shows that faster switching significantly reduces not only the inductor value but also volume, price, and even the inductor losses. In addition, unlike conventional resonant concepts, soft-switching control as part of the proposed PRC eliminates input voltage-dependent losses over a wide operating range, resulting in 76.3% peak efficiency. At Vin = 48 V, a loss reduction of 35% is achieved compared with the conventional buck converter. Adjusting an integrated capacitor array, and selecting the number of oscillation periods, keeps the switching frequency within a narrow range. This ensures high efficiency across a wide range of Vin = 12–48 V, 100–500-mA load, and 5-V output at up to 25-MHz switching frequency. Thanks to the low output current ripple, the output capacitor can be as small
as 50 nF.
This paper presents a fully integrated gate driver in a 180-nm bipolar CMOS DMOS (BCD) technology with 1.5-A max. gate current, suitable for normally OFF gallium nitride (GaN) power switches, including gate-injection transistors (GIT). Full-bridge driver architecture provides a bipolar and three-level gate drive voltage for a robust and efficient GaN switching. The concept of high voltage energy storing (HVES), which comprises an on-chip resonant LC tank, enables a very area-efficient buffer capacitor integration and superior gatedriving speed. It reduces the component count and the influence of parasitic gate-loop inductance. Theory and calculations confirm the benefits of HVES compared to other capacitor implementation methods. The proposed gate driver delivers a gate charge of up to 11.6 nC, sufficient to drive most types of currently available GaN power transistors. Consequently, HVES enables to utilize the fast switching capabilities of GaN for advanced and compact power electronics.
Boost converters suffer from a bandwidth limitation caused by the right-half plane zero (RHPZ), which occurs in the control-to-output transfer function. In contrast, there are many applications that require superior dynamic behavior. Further, size and cost of boost converter systems can be minimized by reduced voltage deviations and fast transient responses in case of large signal load transients. The key idea of the proposed ΔV/Δt-intervention control concept is to adapt the controller output to its new steady state value immediately after a load transient by prediction from known parameters. The concept is implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology and a Xilinx Spartan-6 field programmable gate array (FPGA). In a boost converter with 3.5V input voltage, 6.3V output voltage, 1.2A load, and 500 kHz switching frequency, the output voltage deviations are 2.8x smaller, scaling down the output capacitor value by the same factor. The recovery times are 2.4x shorter in case of large signal load transients with the proposed concept. The control is widely applicable, as it supports constant switching frequencies and allows for duty cycle and inductor current limitations. It also shows various advantages compared to conventional control and to selected adaptive control concepts.
Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ~1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.
A wide-bandwidth galvanically isolated current sensing circuit with an integrated Rogowski coil in 180nm CMOS is presented. Exploiting the high-frequency properties of an optimized on-chip Rogowski coil, currents can be measured up to a bandwidth of 75 MHz. The analog sensor front-end comprises a two-stage integrator, which allows a chopper frequency below signal bandwidth, resulting in 2.2 mVrms output noise. An additional integrated Hall sensor extends the measurement range towards DC.
The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high speed and power-efficient level shifter for voltages of up to 50V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv / dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40% compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180nm BiCMOS technology. Measurements confirm a 50V 120MHz high-speed operation of the level shifter with a rising / falling propagation delay of 1.45 ns / 1.3 ns, respectively. The dv / dt robustness has been confirmed by measurements for transitions up to 6V/ ns.
This paper presents a digitally controlled boost converter IC for high output voltage and fast transient applications. Thus, it is well applicable in automotive and industrial environments. The 3V-to-6V input voltage, 6.3V output voltage, 1A boost converter IC is fabricated in a 180nm BCD technology. Digital control enables cost savings, advanced control concepts, and it is less parameter sensitive compared to common analog control. A 90 ns latency, 6-bit delay line ADC operates with a window concept, meeting high resolution requirements, e.g. in car battery applications. An output voltage live tracking is included for extending the ADC conversion window. A charge pump DAC provides high resolution, monotonicity, and short 128 ns conversion time. Further, a standard digital PI controller is enhanced by a simple but effective ΔV/Δt-intervention control. It results in 2.8x reduced output voltage deviations in case of load steps, scaling down the output capacitor value by the same factor.
This paper addresses what we call the investment question: under what plausible circumstances, if any, can variable renewable energy (VRE, and solar photovoltaic (PV) in particular) be a good investment? Although VRE has been growing rapidly world-wide, it is generally subsidized. Under what cost and market conditions can solar PV flourish without subsidy? We employ solar insolation and market price data from the U.S. and from Germany to gain insight into the investment question. We find that unsubsidized solar PV is or may soon be a justifiable investment, but that market arrangements may play a crucial role in determining success. We end by sketching a proposal that amounts to a reformed capacity market that would afford participation of solar PV.
This work is a report on practical experiences with the issue of interoperability in German practice management systems (PMSs) from an ongoing clinical trial on teledermatology, the TeleDerm project. A proprietary and established web-platform for store-and-forward telemedicine is integrated with the IT in the GPs’ offices for automatic exchange of basic patient data. Most of the 19 different PMSs included in the study sample lack support of modern health data exchange standards, therefore the relatively old but widely available German health data exchange interface “Gerätedatentransfer” (GDT) is used. Due to the lack of enforcement and regulation of the GDT standard, several obstacles to interoperability are encountered. As a partial, but reusable working solution to cope with these issues, we present a custom middleware which is used in conjunction with GDT. We describe the design, technical implementation and observed hindrances with the existing infrastructure. A discussion on health care interfacing standards and the current state of interoperability in German PMS software is given.
A fully passive RFID temperature sensor SoC with an accuracy of ±0.4°C (3σ) from 0°C to 125°C
(2018)
This paper presents a fully passive 13.56 MHz RFID temperature sensor system-on-chip. Its power management unit (PMU) operates over a large temperature range using a zero temperature coefficient (TC) bias source. On-chip temperature sensing is accomplished with low voltage, low power CMOS circuitry and time-domain signal processing. Two operating modes have been defined to study supply noise sensitivity: command mode and listening mode, which represent sensor operation during RFID command transfer and listening, respectively. Besides a standard readout command, a customized serial readout command is utilized to distinguish the data from both modes. In command mode, the sensor suffers from interference from the RFID command packet and outputs interference as well, while the sensor outputs no interference in listening mode. Measurements show that sensor resolution in listening mode is improved by a factor of approximately 16 compared to command mode. The chip was fabricated in a standard 0.35 µm CMOS technology and chip-on-board mounted to a tuned RFID transponder coil on an aluminium core FRA4 PCB substrate. Real-time wireless temperature sensing has been demonstrated with a commercial HF RFID reader. With a two-point calibration, the SoC achiesves a 3σ sensing accuracy of ±0.4°C from 0° C to 125° C.
Micro grids often consist of energy generators, storages and consumers with controllers which are not prepared for their integration into communication networks for energy systems. In this paper it will be presented, how standards from the field of energy automation can be applied in such controllers. The data for communication interfaces can be structured according to the IEC 61850- or the VHPREADY standard. It is investigated which requirements must be supported to implement such data models within the controllers. For the transmission of the data we propose the OPC UA protocol, which supports extensive security measures and which is today available for nearly all modern types of controllers and computers.
The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the presented integrated micropower supply. Connected to the 120/230-VRMS mains, it provides a 3.3-V ac output voltage, suitable for applications such as the Internet-of Things and smart homes. The micropower supply consists of a fully integrated ac–dc and dc–dc converter with one external low-voltage surface mount device buffer capacitor, resulting in an extremely compact size. Fabricated in a low-cost 0.35-μm 700-V complimentary metal-oxide-semiconductor technology, it covers a die size of 7.7 mm². The ac–dc converter is a direct coupled, full-wave rectifier with a subsequent series regulator. The dc–dc stage is a fully integrated capacitive 4:1 converter with up to 17-V input and 47.4% peak efficiency. The power supply comprises several high-voltage control circuits including level shifters and various types of charge pumps (CPs). A source supplied CP is utilized that supports a varying switching node potential. The overall losses are discussed and optimized, including flying capacitor bottom-plate losses. The power supply achieves an output power of 3 mW, resulting in a power density of 390 μW/mm². This exceeds prior art by a factor of 11.
Latest advancements in new technologies have made it possible to fully automate the in-plant material flow of small load carriers between the warehouse and the production or assembly line. However, none of methods available in literature fully addresses the planning and dimensioning problem of a logistic system based on these new autonomous technologies. This paper is set to present a method to estimate the fleet size of the new logistic system. After an overview on the state of the art, the method based on combinatorics and probability theory will be explained. A short discussion and suggestions for forthcoming research will conclude the paper.
Engineers of the research project “Digital Product Life-Cycle” are using a graph-based design language to model all aspects of the product they are working on. This abstract model is the base for all further investigations, developments and implementations. In particular at early stages of development, collaborative decision making is very important. We propose a semantic augmented knowledge space by means of mixed reality technology, to support engineering teams. Therefore we present an interaction prototype consisting of a pico projector and a camera. In our usage scenario engineers are augmenting different artefacts in a virtual working environment. The concept of our prototype contains both an interaction and a technical concept. To realise implicit and natural interactions, we conducted two prototype tests: (1) A test with a low-fidelity prototype and (2) a test by using the method Wizard of Oz. As a result, we present a prototype with interaction selection using augmentation spotlighting and an interaction zoom as a semantic zoom.
The high system flexibility necessary for the full automation of complex and unstructured tasks leads to increased complexity, thus higher costs. On the other hand, the effectiveness and performance of such systems decrease, explaining the unfulfilled potential of robotcs in sectors such as intralogistics, where the benefits of a robotic solution rarely justify its costs. Taking the distance from the false idea that a task should be either fully automated, or fully manual, this aper presents a method for design of a lean human-robot interaction (HRI) withe the objective of the "right level of automation", where functions are divided among human and automated agends, so that the overall process gains in performances and/or costs. ... The 10 progressive steps of the method are presented and discussed with reference to their graphical tool: the House of Quality Interaction.
A simple determination of the error voltage compensation map for motor parameter identification
(2018)
This paper proposes a new method for determining the error voltage compensation map in a parameter identification procedure of three-phase induction motors with an inverter. The compensation curve depending on the motor current is determined using a simple procedure based on given reference voltage steps and the corresponding steady state values of the stator current of the induction motor.
Milk-run systems are becoming more and more popular when it comes to in-plant material supply. Planning and dimensioning such a system poses challenges, which are difficult to overcome, especially in scenarios characterized by a large number of hard constraints and by well-established processes. This paper is set to ease the task of the planner by presenting an innovative flexible method for the planning and dimensioning of in-plant milk-run systems in high constrained scenarios. After an overview on tugger train systems and existing planning methods, an extensive description of the new method will be given. The new method proposed will be critically analyzed and discussed before suggesting forthcoming research.
Software engineering courses have to deliver theoretical and technical knowledge and skills while establishing links to practice. However, due to course goals or resource limitations, it is not always possible or even meaningful to set up complete projects and let students work on a real piece of software. For instance, if students shall understand the impact of group dynamics on productivity, a particular software to be developed is of less interest than an environment in which students can learn about team-related phenomena. To address this issue, we use experimentation as a teaching tool in software engineering courses. Experiments help to precisely characterize and study a problem in a systematic way, to observe phenomena, and to develop and evaluate solutions. Furthermore, experiments help establishing short feedback and learning cycles, and they also allow for experiencing risk and failure scenarios in a controlled environment. In this paper, we report on three courses in which we implemented different experiments and we share our experiences and lessons learned. Using these courses, we demonstrate how to use classroom experiments, and we provide a discussion on the feasibility based on formal and informal course evaluations. This experience report thus aims to help teachers integrating small- and medium sized experiments in their courses.
An assessment model to foster the adoption of agile software product lines in the automotive domain
(2018)
A software product line is commonly used for the software development in large automotive organizations. A strategic reuse of software is needed to handle the increasing complexity of the development and to maintain the quality of numerous software variants. However, the development process needs to be continuously adapted at a fast pace to satisfy the changing market demands. Introducing agile software development methods promise the flexibility to react on customers’ change requests and market demands to deliver high quality software. Despite this need, it is still challenging to combine agile software development and product lines. The maturity of an agile adoption is often hard to determine. Assessing the current situation regarding the combination is a first step towards a successful inclusion of agile methods into automotive software product lines. Based on an interview study with 16 participants and a literature review, we build the so-called ASPLA Model allowing self-assessments within the team to determine the current state of agile software development in combination with software product lines. The model comprises seven areas of improvement and recommends a possibility to improve the current status.