620 Ingenieurwissenschaften und Maschinenbau
Refine
Document Type
- Conference proceeding (21)
- Journal article (5)
- Book chapter (3)
- Book (1)
Is part of the Bibliography
- yes (30)
Institute
- Technik (30)
Publisher
Analog integrated circuit sizing still relies heavily on human expert knowledge as previous automation approaches have not found wide-spread acceptance in industry. One strand, the optimization-based automation, is often discarded due to inflated constraining setups, infeasible results or excessive run times. To address these deficits, this work proposes a alternative optimization flow featuring a designer’s intuition for feasible design spaces through integration of expert knowledge based on the gm/ID-method. Moreover, the extensive run times of simulation-based optimization flows are overcome by incorporating computationally efficient machine learning methods. Neural network surrogate models predicting eleven performance parameters increase the evaluation speed by 3 400× on average compared to a simulator. Additionally, they enable the use of optimization algorithms dependent on automatic differentiation, that would otherwise be unavailable in this field. First, an up to 4× more efficient way for sampling training data based on the aforementioned space is detailed. After presenting the architecture and training effort regarding the surrogate models, they are employed as part of the objective function for sizing three operational amplifiers with three different optimization algorithms. Additionally, the benefits of using the gm/ID-method become evident when considering technology migration, as previously found solutions may be reused for other technologies.
This paper presents a machine learning powered, procedural sizing methodology based on pre-computed look-up tables containing operating point characteristics of primitive devices. Several Neural Networks are trained for 90nm and 45nm technologies, mapping different electrical parameters to the corresponding dimensions of a primitive device. This transforms the geometric sizing problem into the domain of circuit design experts, where the desired electrical characteristics are now inputs to the model. Analog building blocks or entire circuits are expressed as a sequence of model evaluations, capturing the sizing strategy and intention of the designer in a procedure, which is reusable across different technology nodes. The methodology is employed for the sizing of two operational amplifiers, and evaluated for two technology nodes, showing the versatility and efficiency of this approach.
We discuss the fabrication technologies for IC chips in this chapter. We will focus on the main process steps and especially on those aspects that are of particular importance for understanding how they affect, and in some cases drive, the layout of ICs. All our analyses in this chapter will be for silicon as the base material; the principles and understanding gained can be applied to other substrates as well. Following a brief introduction to the fundamentals of IC fabrication (Sect. 2.1) and the base material used in it, namely silicon (Sect. 2.2), we discuss the photolithography process deployed for all structuring work in Sect. 2.3. We will then present in Sect. 2.4 some theoretical opening remarks on typical phenomena encountered in IC fabrication. Knowledge of these phenomena is very useful for understanding the process steps we cover in Sects. 2.5–2.8. We examine a simple exemplar process in Sect. 2.9 and observe how a field-effect transistor (FET) – the most important device in modern integrated circuits—is created. To drive the key points home, we provide a review of each topic at the end of every section from the point of view of layout design by discussing relevant physical design aspects.
IC layout automation with self-organized wiring and arrangement of responsive modules (SWARM)
(2019)
Focused on automating analog IC layout, the multi-agent-system Self-organized Wir ing and Arrangement of Responsive Modules (SWARM) combines the powers of pro-cedural generators and algorithmic optimization into a novel bottom-up meets top-down flow of supervised layout module interaction. Provoking self-organization via the effect of emergence, examples show SWARM finding even optimal placement solutions and producing constraint-compliant layout blocks which fit into a specified zone.
In this paper, we address the novel EDP (Expert Design Plan) principle for procedural design automation of analog integrated circuits, which captures the knowledge-based design strategy of human circuit designers in an executable script, making it reusable. We present the EDP Player, which enables the creation and execution of EDPs for arbitrary circuits in the Cadence® Virtuoso® Design Environment. The tool provides a generic version of an instruction set, called EDPL (EDPLanguage), enabling emulation of a typical manual analog sizing flow. To automate the design of a Miller Operational Amplifier and to create variants of a Smart Power IC, several EDPs were implemented using this tool. Employing these EDPs leads to a strong reduction of design time without compromising design quality or reliability.
Anders als Digital-ICs, die hochautomatisiert entworfen werden können, ist der Entwurf analoger ICs bis heute Handarbeit. Übliche auf Optimierung basierende Automatisierungsverfahren scheitern. Die Ursachen wurden jetzt in einem Forschungsprojekt untersucht, um neue Ansätze zur Entwurfsautomatisierung analoger ICs abzuleiten.
This book covers the fundamental knowledge of layout design from the ground up, addressing both physical design, as generally applied to digital circuits, and analog layout. Such knowledge provides the critical awareness and insights a layout designer must possess to convert a structural description produced during circuit design into the physical layout used for IC/PCB fabrication.
Nowadays, the demand for a MEMS development/design kit (MDK) is even more in focus than ever before. In order to achieve a high quality and cost effectiveness in the development process for automotive and consumer applications, an advanced design flow for the MEMS (micro electro mechanical systems) element is urgently required. In this paper, such a development methodology and flow for parasitic extraction of active semiconductor devices is presented. The methodology considers geometrical extraction and links the electrically active pn junctions to SPICE standard library models and subsequently extracts the netlist. An example for a typical pressure sensor is presented and discussed. Finally, the results of the parasitic extraction are compared with fabricated devices in terms of accuracy and capability.
Due to the lack of sophisticated component libraries for microelectromechanical systems (MEMS), highly optimized MEMS sensors are currently designed using a polygon driven design flow. The advantage of this design flow is its accurate mechanical simulation, but it lacks a method for an efficient and accurate electrostatic analysis of parasitic effects of MEMS. In order to close this gap in the polygon-driven design flow, we present a customized electrostatic analysis flow for such MEMS devices. Our flow features a 2.5D fabrication-process simulation, which simulates the three typical MEMS fabrication steps (namely deposition of materials including topography, deep reactive-ion etching, and the release etch by vapor-phase etching) very fast and on an acceptable abstraction level. Our new 2.5D fabrication-process simulation can be combined with commercial field-solvers such as they are commonly used in the design of integrated circuits. The new process simulation enables a faster but nevertheless satisfactory analysis of the electrostatic parasitic effects, and hence simplifies the electrical optimization of MEMS.