620 Ingenieurwissenschaften und Maschinenbau
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Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming tasks of todays complex system on chip (SoC) designs. In contrast to digital system design, AMS designers have to deal with a continuous state space of conservative quantities, highly nonlinear relationships, non-functional influences, etc. enlarging the number of possibly critical scenarios to infinity. In this special session we demonstrate the verification of functional properties using simulative and formal methods. We combine different approaches including automated abstraction and refinement of mixed-level models, state-space discretization as well as affine arithmetic. To reach sufficient verification coverage with reasonable time and effort, we use enhanced simulation schemes to avoid conventional simulation drawbacks.
Pegelumsetzer mit einem ersten Eingang, der ein erstes Signal erfasst, wobei das erste Signal einen ersten Spannungspegel aufweist, einem Ausgang, der ein zweites Signal erzeugt, wobei das zweite Signal einen zweiten Spannungspegel aufweist, wobei der zweite Spannungspegel größer als der erste Spannungspegel ist und einem Differenzverstärker, der eine Differenzspannung erfasst, wobei der Differenzverstärker mit einer Versorgungsspannung und einer hochseitige Masse verbunden ist, wobei die Versorgungsspannung ein erstes Spannungspotential und die hochseitige Masse ein zweites Spannungspotential aufweist, dadurch gekennzeichnet, dass der erste Eingang mit einer ersten Teilschaltung verbunden ist, wobei die erste Teilschaltung mit einer zweiten Teilschaltung unidirektional verbunden ist, wobei die zweite Teilschaltung mit der Versorgungsspannung und der hochseitigen Masse verbunden ist, wobei die zweite Teilschaltung mindestens zwei Ausgänge aufweist, die die Differenzspannung des Differenzverstärkers erzeugen, wobei über einen Versorgungsspannungseingang und einen hochseitigen Masseeingang eine zusätzliche Spannung einkoppelt und der Differenzverstärker das zweite Signal in Abhängigkeit der Differenzspannung, der Versorgungsspannung, der hochseitigen Masse und der zusätzlichen Spannung erzeugt.
Die vorliegende Erfindung betrifft ein Verfahren zur Regelung einer Totzeit in einem Synchronwandler (100), in welchem ein zyklisches Schalten eines Steuerschalters (2) und eines Synchronschalters (3) erfolgen, wobei der Steuerschalter (2) mittels eines ersten Schaltsignals (S1) und der Synchronschalter (3) mittels eines zweiten Schaltsignals (S2) geschaltet werden. Das Verfahren umfasst ein Erfassen und Vorhalten eines Spannungswertes, welcher eine Spannung (VSW) über den Synchronschalter (3) zu einem bestimmten Zeitpunkt beschreibt, und ein Anpassen des ersten und/oder zweiten Schaltsignals (S1, S2) für einen folgenden Zyklus basierend auf dem vorgehaltenen Spannungswert.
An integrated synchronous buck converter with a high resolution dead time control for input voltages up to 48V and 10MHz switching frequency is presented. The benefit of an enhanced dead time control at light loads to enable zero voltage switching at both the high-side and low-side switch at low output load is studied. This way, compact multi-MHz DCDC converters can be implemented at high efficiency over a wide load current range. The concept also eliminates body diode forward conduction losses and minimizes reverse recovery losses. A dead time resolution of 125 ps is realized by an 8-bit differential delay chain. A further efficiency enhancement by soft switching at the high-side switch at light load is achieved with a voltage boost of the switching node by dead time control in forced continuous conduction mode. The monolithic converter is implemented in an 180nm high-voltage BiCMOS technology. At V IN = 48V, V OUT = 5V, 50mA load, 10MHz switching frequency and 500 nH output inductance, the efficiency is measured to be increased by 14.4% compared to a conventional predictive dead time control. A peak efficiency of 80.9% is achieved at 12V input.
Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM verification to robust (pro-active) EM aware design - where the circuit layout is designed with individual EM-robust solutions - is urgently needed. This tutorial will give an overview of EM and its effects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its specific characteristics that can be affected during physical design. Examples of EM countermeasures which are applied in today’s commercial design flows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission proiles to obtain application-oriented current density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post layout EM verification towards an EM aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit’s reliability.
Methods for increasing the energy efficiency of induction motors by an appropriate control strategy have been a subject of research during the last years. Several methods for loss minimization have been developed for induction motors operated in a steady state. In recent years, some solutions for the dynamic case have been given as well either using an online or offline optimization approach, implying a certain computational burden, which is undesired in practice. This paper shows that the appropriate application of steady state techniques during transients due to a changing motor torque is a suboptimal strategy with an acceptable performance for efficiency optimization given an induction machine where saturation effects of the main inductance must be considered. The optimization problem is simplified such that a simple suboptimal solution is possible and the quality of the suboptimal solution is investigated by simulations and measurements. The proposed solution is simple, easy to implement, and does not require an online optimization. In addition, the influence of magnetizing induction saturation is considered.
This paper introduces a novel placement methodology for a common-centroid (CC) pattern generator. It can be applied to various integrated circuit (IC) elements, such as transistors, capacitors, diodes, and resistors. The proposed method consists of a constructive algorithm which generates an initial, close to the optimum, solution, and an iterative algorithm which is used subsequently, if the output of constructive algorithm does not satisfy the desired criteria. The outcome of this work is an automatic CC placement algorithm for IC element arrays. Additionally, the paper presents a method for the CC arrangement evaluation. It allows for evaluating the quality of an array, and a comparison of different placement methods.
The hotspot detection has received much attention in the recent years due to a substantial mismatch between lithography wavelength and semiconductor technology feature size. This mismatch causes diffraction when transferring the layout from design onto a silicon wafer. As a result, open or short circuits (i.e. lithography hotspots) are more likely to be produced. Additionally, increasing numbers of semiconductors devices on a wafer required more time for the lithography hotspot detection analysis. In this work, we propose a fast and accurate solution based on novel artificial neural network (ANN) architecture for precise lithography hotspot detection using a convolution neural network (CNN) adopting a state of-the-art technique. The experimental results showed that the proposed model gained accuracy improvement over current state-of-theart approaches. The final code has been made publicly available.
Lithographical hotspot (LH) detection using deep learning (DL) has received much attention in the recent years. It happens mainly due to the facts the DL approach leads to a better accuracy over the traditional, state-of-the-art programming approaches. The purpose of ths study is to compare existing data augmentation (DA) techniques for the integrated circuit (IC) mask data using DL methods. DA is a method which refers to the process of creating new samples similar to the training set, thereby helping to reduce the gap between classes as well as improving the performance of the DL system. Experimental results suggest that the DA methods increase overall DL models performance for the hotspot detection tasks.