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DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.
Lehr- und Übungsbuch sowie Nachschlagewerk zur CAD-Software Creo Parametric und zu den Grundlagen der Produktdatenverwaltung mit Windchill. Vermittelt werden die Volumenmodellierung, die 3D Flächenmodellierung, die Blechmodellierung, die Baugruppen- und Zeichnungserstellung, das Erstellen von Animationen, die Definition und Anwendung kinematischer sowie dynamischer Analysen und die Definition von Baugruppen, die Konstruktionsvarianten "Top-Down" und "Bottom-Up" sowie die Organisation von Konstruktionsprojekten über Skelett Techniken.
Weiter werden die Grundlagen des Produktdatenmanagements im Konstruktionsbereich unter Windchill vermittelt. Alle Verfahren werden handlungsorientiert an einem weitgehend durchgehenden Modellierungsprojekt erarbeitet. Aufgrund des ausführlichen Inhalts- und Sachwortverzeichnisses sowie einer Vielzahl an Bildern ist das Buch als Grundlage für Vorlesungen, Schulungen oder Praktika und insbesondere auch zum Selbststudium sowie als Nachschlagewerk geeignet.
Lehrbuch zur CAD-Software Creo Parametric und zur Produktdatenverwaltung mit Windchill.
3D-Volumenmodellierung, 3D-Flächenmodellierung, Blechmodellierung, Baugruppen- und Zeichnungserstellung, Definition von Normteilen, Erstellen von Animationen und dynamischen Analysen.
Verfahren zum Umgang mit großen Baugruppen und zur flexiblen Modellierung, Konstruk-tionsvarianten "Top-Down" und "Bottom-Up", Organisation von Konstruktionsprojekten über Skeletttechnik.
Neu: Konstruktion von und mit Mehrkörperobjekten, Rahmenkonstruktion in der Profilumgebung (AFX), intelligente Verbindungen (IFX), Live Simulation und Generatives Design.
We present the results of an extensive characterization of the performance and stability of a third-order continuous-time delta-sigma modulator with active coefficient error compensation. Using our previously published coefficient tuning technique, process variation induced R-C time-constant (TC) errors in the forward signal path can be compensated indirectly using continuously tunable DACs in the feedback path. To validate our technique experimentally with a range of real TC variations, we designed a modulator with discretely configurable integration capacitor arrays in a 0.35-μm CMOS process. We configured the capacitors of the fabricated device for a range of total TC variations from -28.4 % to +19.3 % and measured the signal-to-noise ratio (SNR) as a function of the input amplitude before and after compensating the variations electrically using the feedback DACs. The results show that our tuning technique is capable of restoring the desired nominal modulator performance over the entire parameter variation range, including the system’s nominal maximum stable amplitude (MSA).
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. This leads especially at a high input voltage to a decreasing efficiency caused by switching losses. Conventional calculations are not suitable to predict the efficiency as parasitic capacitances have a significant loss contribution. This paper presents an analytical efficiency model which considers parasitic capacitances separately and calculates the power loss contribution of each capacitance to any resistive element. The proposed model is utilized for efficiency optimization of converters with switching frequencies >10MHz and input voltages up to 40V. For experimental evaluation a DCDC converter was manufactured in a 180 nm HV BiCMOS technology. The model matches a transistor level simulation and measurement results with an accuracy better than 3.5 %. The accuracy of the parasitic capacitances of the high voltage transistor determines the overall accuracy of the efficiency model. Experimental capacitor measurements can be fed into the model. Based on the model, different architectures have been studied.
The presented wide-Vin step-down converter introduces a parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300 nH resonant coil, placed in parallel to a conventional buck converter. Unlike conventional resonant concepts, the implemented soft-switching control eliminates input voltage dependent losses over a wide operating range. This ensures high efficiency across a wide range of Vin= 12-48V, 100-500mA load and 5V output at up to 15MHz switching frequency. The peak efficiency of the converter is 76.3 %. Thanks to the low output current ripple, the output capacitor can be as small as 50 nF, while the inductor tolerates a larger ESR, resulting in small component size. The proposed PRC architecture is also suitable for future power electronics applications using fast-switching GaN devices.
This paper presents a wide-Vin step-down parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300-nH resonant coil, placed in parallel to a conventional buck converter. Soft-switching resonant converters are beneficial for high-Vin multi-MHz converters to reduce dominant switching losses, enabling higher switching frequencies. The output filter inductor is optimized based on an empirical study of available inductors. The study shows that faster switching significantly reduces not only the inductor value but also volume, price, and even the inductor losses. In addition, unlike conventional resonant concepts, soft-switching control as part of the proposed PRC eliminates input voltage-dependent losses over a wide operating range, resulting in 76.3% peak efficiency. At Vin = 48 V, a loss reduction of 35% is achieved compared with the conventional buck converter. Adjusting an integrated capacitor array, and selecting the number of oscillation periods, keeps the switching frequency within a narrow range. This ensures high efficiency across a wide range of Vin = 12–48 V, 100–500-mA load, and 5-V output at up to 25-MHz switching frequency. Thanks to the low output current ripple, the output capacitor can be as small
as 50 nF.
A highly integrated synchronous buck converter with a predictive dead time control for input voltages >18 V with 10 MHz switching frequency is presented. A high resolution dead time of ˜125 ps allows to reduce dead time dependent losses without requiring body diode conduction to evaluate the dead time. High resolution is achieved by frequency compensated sampling of the switching node and by an 8 bit differential delay chain. Dead time parameters are derived in a comprehensive study of dead time depended losses. This way, the efficiency of fast switching DC-DC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching. High-speed circuit blocks for fast switching operation are presented including level shifter, gate driver, PWM generator. The converter has been implemented in a 180 nm high-voltage BiCMOS technology.
This publication gives a short introduction and overview of the European project SCOUT and introduces a methodology for a holistic approach to record the state of the art in technical (vehicle and connectivity, human factors regarding physiologic and ergonomic level) and non-technical enablers (societal, economic, legal, regulatory and policy level) of connected and automated driving in Europe. The paper addresses beside the technical topics of environmental perception, E/E architecture, actuators and security, the state of the art of the legal framework in the context of connected and automated driving.